initial commmit
This commit is contained in:
Schrom01
commit
cf207b819a
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
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<nMigrate>0</nMigrate>
|
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</Extensions>
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<DaveTm>
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<dwLowDateTime>0</dwLowDateTime>
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<dwHighDateTime>0</dwHighDateTime>
|
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</DaveTm>
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|
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<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
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<BeepAtEnd>1</BeepAtEnd>
|
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<RunSim>0</RunSim>
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<RunTarget>1</RunTarget>
|
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<RunAbUc>0</RunAbUc>
|
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</OPTTT>
|
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<OPTHX>
|
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<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
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<HexRangeLowAddress>0</HexRangeLowAddress>
|
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<HexRangeHighAddress>0</HexRangeHighAddress>
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<HexOffset>0</HexOffset>
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</OPTHX>
|
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<OPTLEX>
|
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<PageWidth>79</PageWidth>
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<PageLength>66</PageLength>
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<TabStop>8</TabStop>
|
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<ListingPath>.\build\</ListingPath>
|
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</OPTLEX>
|
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<ListingPage>
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<CreateCListing>1</CreateCListing>
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<CreateAListing>1</CreateAListing>
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<CreateLListing>1</CreateLListing>
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<CreateIListing>0</CreateIListing>
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<AsmCond>1</AsmCond>
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<AsmSymb>1</AsmSymb>
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<CCond>1</CCond>
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<CCode>0</CCode>
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<CListInc>0</CListInc>
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<CSymb>0</CSymb>
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<LinkerCodeListing>0</LinkerCodeListing>
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</ListingPage>
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<OPTXL>
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<LMap>1</LMap>
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<LComments>1</LComments>
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<LGenerateSymbols>1</LGenerateSymbols>
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<LLibSym>1</LLibSym>
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<LLines>1</LLines>
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<LLocSym>1</LLocSym>
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<LPubSym>1</LPubSym>
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<LXref>0</LXref>
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<LExpSel>0</LExpSel>
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</OPTXL>
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<OPTFL>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>18</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
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<tRwatch>1</tRwatch>
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<tRmem>1</tRmem>
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<tRfunc>0</tRfunc>
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<tRbox>1</tRbox>
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<tRtrace>1</tRtrace>
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<sRSysVw>1</sRSysVw>
|
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<tRSysVw>1</tRSysVw>
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<sRunDeb>0</sRunDeb>
|
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<sLrtime>0</sLrtime>
|
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<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
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<bTchkAxf>0</bTchkAxf>
|
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<nTsel>6</nTsel>
|
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<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
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<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ST-LINKIII-KEIL_SWO</Key>
|
||||
<Name>-U-O206 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>app</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
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||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\app\main.s</PathWithFileName>
|
||||
<FilenameWithoutPath>main.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
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<FileNumber>2</FileNumber>
|
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<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
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<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\app\utils.s</PathWithFileName>
|
||||
<FilenameWithoutPath>utils.s</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
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<GroupNumber>1</GroupNumber>
|
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<FileNumber>3</FileNumber>
|
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<FileType>2</FileType>
|
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<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\app\measurement.s</PathWithFileName>
|
||||
<FilenameWithoutPath>measurement.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::HAL</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,529 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pArmCC>6180000::V6.18::ARMCLANG</pArmCC>
|
||||
<pCCUsed>6180000::V6.18::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>CT_Board_HS14_M0</Device>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<PackID>InES.CTBoard14_DFP.4.0.2</PackID>
|
||||
<PackURL>https://ennis.zhaw.ch/pack/</PackURL>
|
||||
<Cpu>IROM(0x08000000,0x200000) IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile></RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:CT_Board_HS14_M0$SVD\STM32F429x.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>Lab</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
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||||
<DebugInformation>1</DebugInformation>
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||||
<BrowseInformation>1</BrowseInformation>
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||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
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||||
<Merge32K>0</Merge32K>
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||||
<CreateBatchFile>0</CreateBatchFile>
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<BeforeCompile>
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||||
<RunUserProg1>0</RunUserProg1>
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||||
<RunUserProg2>0</RunUserProg2>
|
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<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
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<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
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<UserProg1Name></UserProg1Name>
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||||
<UserProg2Name></UserProg2Name>
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||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
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||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
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||||
<RunUserProg1>0</RunUserProg1>
|
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<RunUserProg2>0</RunUserProg2>
|
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<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments>-MPU </SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments>-MPU </TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>2</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--diag_suppress 6314</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>app</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\app\main.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>utils.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\app\utils.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>measurement.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\app\measurement.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::HAL</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<packages>
|
||||
<filter>
|
||||
<targetInfos/>
|
||||
</filter>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.1">
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
</packages>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0">
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL">
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL">
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL">
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL">
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" supportContact="https://ennis.zhaw.ch/" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="Device\Source\datainit_ctboard.s" version="4.0.1">
|
||||
<instance index="0">RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\Source\startup_ctboard.s" version="4.0.1">
|
||||
<instance index="0">RTE\Device\CT_Board_HS14_M0\startup_ctboard.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\Source\system_ctboard.c" version="4.0.1">
|
||||
<instance index="0">RTE\Device\CT_Board_HS14_M0\system_ctboard.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="HAL\Source\hal_fmc.c" version="3.0.1">
|
||||
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_fmc.c</instance>
|
||||
<component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="HAL\Source\hal_gpio.c" version="4.0.1">
|
||||
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_gpio.c</instance>
|
||||
<component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="HAL\Source\hal_pwr.c" version="2.2.0">
|
||||
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_pwr.c</instance>
|
||||
<component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="HAL\Source\hal_rcc.c" version="4.0.1">
|
||||
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_rcc.c</instance>
|
||||
<component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
|
||||
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
;* ----------------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ----------------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT1 - Lab 12
|
||||
;* -- Description : Read potentiometer and generate analog voltage
|
||||
;* --
|
||||
;* -- 1) Setup ADC for reading analog voltage of potentiometer
|
||||
;* -- 2) Setup DAC for generating analog voltage signal
|
||||
;* --
|
||||
;* -- $Id: analog.s 1016 2014-11-28 07:27:21Z feur $
|
||||
;* ----------------------------------------------------------------------------
|
||||
|
||||
IMPORT set_sfr
|
||||
IMPORT clear_sfr
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Constants
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myCode, CODE, READONLY
|
||||
|
||||
THUMB
|
||||
|
||||
REG_RCC_AHB1ENR EQU 0x40023830
|
||||
REG_RCC_APB1ENR EQU 0x40023840
|
||||
REG_RCC_APB2ENR EQU 0x40023844
|
||||
|
||||
REG_GPIOA_MODER EQU 0x40020000
|
||||
REG_GPIOA_OSPEEDR EQU 0x40020008
|
||||
REG_GPIOA_PUPDR EQU 0x4002000c
|
||||
REG_GPIOF_MODER EQU 0x40021400
|
||||
|
||||
REG_ADC3_SR EQU 0x40012200
|
||||
REG_ADC3_CR1 EQU 0x40012204
|
||||
REG_ADC3_CR2 EQU 0x40012208
|
||||
REG_ADC3_SMPR2 EQU 0x40012210
|
||||
REG_ADC3_SQR1 EQU 0x4001222c
|
||||
REG_ADC3_SQR3 EQU 0x40012234
|
||||
REG_ADC3_DR EQU 0x4001224c
|
||||
|
||||
REG_DAC_CR EQU 0x40007400
|
||||
REG_DAC_DHR8R1 EQU 0x40007410
|
||||
|
||||
REG_EXTI_IMR EQU 0x40013c00
|
||||
REG_EXTI_RTSR EQU 0x40013c08
|
||||
REG_EXTI_FTSR EQU 0x40013c0c
|
||||
|
||||
REG_NVIC_ISER0 EQU 0xe000e100
|
||||
REG_NVIC_ICER0 EQU 0xe000e180
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Initialize ADC and DAC
|
||||
; -----------------------------------------------------------------------------
|
||||
init_analog PROC
|
||||
EXPORT init_analog
|
||||
|
||||
PUSH {R6-R7, LR}
|
||||
|
||||
init_adc ; Clock configuration
|
||||
LDR R6, =REG_RCC_AHB1ENR
|
||||
LDR R7, =0x20 ; Enable GPIOF clock
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_RCC_APB2ENR
|
||||
LDR R7, =0x400 ; Enable ADC3 clock
|
||||
BL set_sfr
|
||||
|
||||
; Analog pin configuration (PF.6)
|
||||
LDR R6, =REG_GPIOF_MODER
|
||||
LDR R7, =0x3000
|
||||
BL set_sfr
|
||||
|
||||
; ADC configuration
|
||||
LDR R6, =REG_ADC3_CR1
|
||||
LDR R7, =0x2000000 ; 8 bit resolution
|
||||
; Disable scan mode
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_ADC3_CR2
|
||||
LDR R7, =0x3 ; Enable continous conv. mode
|
||||
; Enable ADC
|
||||
BL set_sfr
|
||||
|
||||
; Select channel to read from
|
||||
LDR R6, =REG_ADC3_SMPR2
|
||||
LDR R7, =0x6000 ; ch4: 144 cycles sampling time
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_ADC3_SQR3
|
||||
LDR R7, =0x4 ; ch4: rank 1 (?)
|
||||
BL set_sfr
|
||||
|
||||
|
||||
init_dac ; Clock configuration
|
||||
LDR R6, =REG_RCC_AHB1ENR
|
||||
LDR R7, =0x1 ; Enable GPIOA clock
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_RCC_APB1ENR
|
||||
LDR R7, =0x20000000 ; Enable DAC clock
|
||||
BL set_sfr
|
||||
|
||||
; Analog pin configuration (PA.4)
|
||||
LDR R6, =REG_GPIOA_MODER
|
||||
LDR R7, =0x300
|
||||
BL set_sfr
|
||||
|
||||
; DAC configuration
|
||||
LDR R6, =REG_DAC_CR
|
||||
LDR R7, =0x1 ; Enable ch. 1
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_DAC_DHR8R1
|
||||
LDR R7, =0x0 ; Set initial value (=0)
|
||||
BL set_sfr
|
||||
|
||||
; Return
|
||||
POP {R6-R7, PC}
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Process reading ADC and outputing via DAC
|
||||
; -----------------------------------------------------------------------------
|
||||
do_analog PROC
|
||||
EXPORT do_analog
|
||||
|
||||
PUSH {R0-R2, R6, LR}
|
||||
|
||||
BL get_adc ; Get ADC value in R7
|
||||
BL set_dac ; Set DAC value from R7
|
||||
|
||||
POP {R0-R2, R6, PC} ; Restore registers and return
|
||||
|
||||
ENDP ; Return
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Convert with ADC an return value
|
||||
; - converted analog value in R7
|
||||
; -----------------------------------------------------------------------------
|
||||
get_adc PROC
|
||||
EXPORT get_adc
|
||||
|
||||
PUSH {R0-R2, R6, LR}
|
||||
|
||||
LDR R6, =REG_ADC3_CR2
|
||||
LDR R7, =0x40000000 ; Start conversion
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_ADC3_SR
|
||||
adc_wait LDR R1, =0x2
|
||||
LDR R2, [R0]
|
||||
BICS R1, R1, R2 ; Is conversion finished
|
||||
BNE adc_wait
|
||||
|
||||
LDR R0, =REG_ADC3_DR
|
||||
LDR R1, [R0] ; Get converted value
|
||||
LDR R7, =0xffff
|
||||
ANDS R7, R7, R1 ; Mask upper halfword
|
||||
|
||||
POP {R0-R2, R6, PC} ; Restore registers and return
|
||||
|
||||
ENDP ; Return
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Set DAC output
|
||||
; - digital value in R7
|
||||
; -----------------------------------------------------------------------------
|
||||
set_dac PROC
|
||||
EXPORT set_dac
|
||||
|
||||
PUSH {R0-R1, R6, LR}
|
||||
|
||||
LDR R6, =REG_DAC_DHR8R1
|
||||
LDR R0, [R6]
|
||||
LDR R1, =0xff
|
||||
BICS R0, R0, R1 ; Clear bits
|
||||
STR R0, [R6]
|
||||
BL set_sfr ; Set value in R7
|
||||
|
||||
POP {R0-R1, R6, PC} ; Restore registers and return
|
||||
|
||||
ENDP ; Return
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -----------------------------------------------------------------------------
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
;* ----------------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ----------------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT1 - Lab 12
|
||||
;* -- Description : Control motor speed and direction
|
||||
;* --
|
||||
;* -- $Id: control.s 1016 2014-11-28 07:27:21Z feur $
|
||||
;* ----------------------------------------------------------------------------
|
||||
|
||||
IMPORT set_sfr
|
||||
IMPORT clear_sfr
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Constants
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myCode, CODE, READONLY
|
||||
|
||||
THUMB
|
||||
|
||||
REG_RCC_AHB1ENR EQU 0x40023830
|
||||
|
||||
REG_GPIOA_MODER EQU 0x40020000
|
||||
REG_GPIOA_OSPEEDR EQU 0x40020008
|
||||
REG_GPIOA_BSRR EQU 0x40020018
|
||||
|
||||
REG_CT_DIPSW EQU 0x60000200
|
||||
|
||||
jump_table DCD case_00, case_01, case_10, case_11
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Initialize EXTI
|
||||
; -----------------------------------------------------------------------------
|
||||
init_control PROC
|
||||
EXPORT init_control
|
||||
|
||||
PUSH {R6-R7, LR}
|
||||
|
||||
init_gpio ; Clock configuration
|
||||
LDR R6, =REG_RCC_AHB1ENR
|
||||
LDR R7, =0x1 ; Enable GPIOA clock
|
||||
BL set_sfr
|
||||
|
||||
; Output pin configuration (PA.5, PA.6)
|
||||
LDR R6, =REG_GPIOA_MODER
|
||||
LDR R7, =0x1400 ; Set pin to output mode
|
||||
BL set_sfr
|
||||
|
||||
LDR R6, =REG_GPIOA_OSPEEDR
|
||||
LDR R7, =0x1400 ; Set pin to high speed
|
||||
BL set_sfr
|
||||
|
||||
; Return
|
||||
POP {R6-R7, PC}
|
||||
|
||||
NOP
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Check buttons
|
||||
; -----------------------------------------------------------------------------
|
||||
do_input PROC
|
||||
EXPORT do_input
|
||||
|
||||
PUSH {R0-R2, LR}
|
||||
|
||||
LDR R0, =REG_CT_DIPSW
|
||||
LDRB R1, [R0]
|
||||
LDR R2, =0x3
|
||||
ANDS R1, R1, R2
|
||||
|
||||
case_switch CMP R1, #4
|
||||
BGE case_00
|
||||
LSLS R1, #2
|
||||
LDR R2, =jump_table
|
||||
LDR R2, [R2, R1]
|
||||
BX R2
|
||||
|
||||
case_00 BL motor_off
|
||||
BL motor_ccw
|
||||
B case_end
|
||||
|
||||
case_01 BL motor_on
|
||||
BL motor_ccw
|
||||
B case_end
|
||||
|
||||
case_10 BL motor_off
|
||||
BL motor_cw
|
||||
B case_end
|
||||
|
||||
case_11 BL motor_on
|
||||
BL motor_cw
|
||||
|
||||
case_end POP {R0-R2, PC}
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Motor control
|
||||
; -----------------------------------------------------------------------------
|
||||
motor_on PROC
|
||||
EXPORT motor_on
|
||||
|
||||
PUSH {R0-R7, LR}
|
||||
|
||||
LDR R0, =REG_GPIOA_BSRR
|
||||
LDR R1, =0x20 ; Set bit 5 -> PA.5
|
||||
STR R1, [R0]
|
||||
|
||||
POP {R0-R7, PC}
|
||||
ENDP
|
||||
|
||||
|
||||
motor_off PROC
|
||||
EXPORT motor_off
|
||||
|
||||
PUSH {R0-R7, LR}
|
||||
|
||||
LDR R0, =REG_GPIOA_BSRR
|
||||
LDR R1, =0x200000 ; Reset bit 5 -> PA.5
|
||||
STR R1, [R0]
|
||||
|
||||
POP {R0-R7, PC}
|
||||
ENDP
|
||||
|
||||
|
||||
motor_cw PROC
|
||||
EXPORT motor_cw
|
||||
|
||||
PUSH {R0-R7, LR}
|
||||
|
||||
LDR R0, =REG_GPIOA_BSRR
|
||||
LDR R1, =0x40 ; Set bit 6 -> PA.6
|
||||
STR R1, [R0]
|
||||
|
||||
POP {R0-R7, PC}
|
||||
ENDP
|
||||
|
||||
|
||||
motor_ccw PROC
|
||||
EXPORT motor_ccw
|
||||
|
||||
PUSH {R0-R7, LR}
|
||||
|
||||
LDR R0, =REG_GPIOA_BSRR
|
||||
LDR R1, =0x400000 ; Reset bit 6 -> PA.6
|
||||
STR R1, [R0]
|
||||
|
||||
POP {R0-R7, PC}
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -----------------------------------------------------------------------------
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
;* ----------------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ----------------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT1 - Lab 12
|
||||
;* -- Description : Reading the User-Button as Interrupt source
|
||||
;* --
|
||||
;* -- $Id: main.s 5082 2020-05-14 13:56:07Z akdi $
|
||||
;* --
|
||||
;* ----------------------------------------------------------------------------
|
||||
|
||||
|
||||
IMPORT init_measurement
|
||||
IMPORT clear_IRQ_EXTI0
|
||||
IMPORT clear_IRQ_TIM2
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Constants
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myCode, CODE, READONLY
|
||||
|
||||
THUMB
|
||||
|
||||
REG_GPIOA_IDR EQU 0x40020010
|
||||
LED_15_0 EQU 0x60000100
|
||||
LED_16_31 EQU 0x60000102
|
||||
REG_CT_7SEG EQU 0x60000114
|
||||
REG_SETENA0 EQU 0xe000e100
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Main
|
||||
; -----------------------------------------------------------------------------
|
||||
main PROC
|
||||
EXPORT main
|
||||
|
||||
|
||||
BL init_measurement
|
||||
|
||||
; Configure NVIC (enable interrupt channel)
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
|
||||
; Initialize variables
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
|
||||
loop
|
||||
; Output counter on 7-seg
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
|
||||
B loop
|
||||
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Handler for EXTI0 interrupt
|
||||
; -----------------------------------------------------------------------------
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Handler for TIM2 interrupt
|
||||
; -----------------------------------------------------------------------------
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
ALIGN
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Variables
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myVars, DATA, READWRITE
|
||||
|
||||
; STUDENTS: To be programmed
|
||||
|
||||
|
||||
; END: To be programmed
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -----------------------------------------------------------------------------
|
||||
END
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
;* ----------------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ----------------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT1 - Lab 12
|
||||
;* -- Description : Meassuring motor speed and direction
|
||||
;* --
|
||||
;* -- 1) Setup external interrupt EXTI for counting motor pulses
|
||||
;* -- 2) Setup TIM2 for generating 1 Hz reference clock
|
||||
;* -- 3) Functions to clear IRQ Flip-flops
|
||||
;* --
|
||||
;* -- $Id: measurement.s 3858 2017-01-09 13:26:26Z kesr $
|
||||
;* ----------------------------------------------------------------------------
|
||||
|
||||
IMPORT set_sfr
|
||||
IMPORT clear_sfr
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Constants
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myCode, CODE, READONLY
|
||||
|
||||
THUMB
|
||||
|
||||
REG_RCC_AHB1ENR EQU 0x40023830
|
||||
REG_RCC_APB1ENR EQU 0x40023840
|
||||
REG_RCC_APB2ENR EQU 0x40023844
|
||||
|
||||
REG_GPIOA_PUPDR EQU 0x4002000c
|
||||
|
||||
REG_EXTI_IMR EQU 0x40013c00
|
||||
REG_EXTI_RTSR EQU 0x40013c08
|
||||
REG_EXTI_PR EQU 0x40013c14
|
||||
|
||||
REG_TIM2_CR1 EQU 0x40000000
|
||||
REG_TIM2_DIER EQU 0x4000000c
|
||||
REG_TIM2_SR EQU 0x40000010
|
||||
REG_TIM2_EGR EQU 0x40000014
|
||||
REG_TIM2_PSC EQU 0x40000028
|
||||
REG_TIM2_ARR EQU 0x4000002c
|
||||
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Initialize EXTI
|
||||
; -----------------------------------------------------------------------------
|
||||
init_measurement PROC
|
||||
EXPORT init_measurement
|
||||
|
||||
PUSH {LR}
|
||||
|
||||
init_exti ; Clock configuration
|
||||
LDR R0, =REG_RCC_AHB1ENR
|
||||
LDR R1, =0x1 ; Enable GPIOA clock
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_RCC_APB2ENR
|
||||
LDR R1, =0x4000 ; Enable SYSCFG clock
|
||||
BL set_sfr
|
||||
|
||||
; Input pin configuration (PA.0)
|
||||
LDR R0, =REG_GPIOA_PUPDR
|
||||
LDR R1, =0x2 ; Set pin to pull-down mode
|
||||
BL set_sfr
|
||||
|
||||
; Configure EXTI
|
||||
LDR R0, =REG_EXTI_IMR
|
||||
LDR R1, =0x1 ; Unmask EXTI0 interrupt
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_EXTI_RTSR
|
||||
LDR R1, =0x1 ; Trigger on rising edge
|
||||
BL set_sfr
|
||||
|
||||
|
||||
init_timer ; Clock configuration
|
||||
LDR R0, =REG_RCC_APB1ENR
|
||||
LDR R1, =0x1 ; Enable TIM2 clock
|
||||
BL set_sfr
|
||||
|
||||
; Configure TIM2 frequency
|
||||
LDR R0, =REG_TIM2_PSC
|
||||
LDR R1, =839 ; Timer prescaler => 84Mhz / 840 = 100kHz => 10us
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_TIM2_ARR
|
||||
LDR R1, =0xffffffff ; Clear Register first, it gets
|
||||
BL clear_sfr ; initialized with 0xffffffff
|
||||
LDR R1, =199998 ; Autoreload value => 99999+1 => 1s
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_TIM2_EGR
|
||||
LDR R1, =0x1 ; Update TIM2 configuration
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_TIM2_DIER
|
||||
LDR R1, =0x1 ; Enable interrupt source
|
||||
BL set_sfr
|
||||
|
||||
LDR R0, =REG_TIM2_CR1
|
||||
LDR R1, =0x1 ; Enable TIM2
|
||||
BL set_sfr
|
||||
|
||||
; Return
|
||||
POP {PC}
|
||||
ENDP
|
||||
|
||||
clear_IRQ_EXTI0 PROC
|
||||
EXPORT clear_IRQ_EXTI0
|
||||
PUSH {LR}
|
||||
LDR R0, =REG_EXTI_PR
|
||||
LDR R1, =0x1 ; Clear irq pending bit
|
||||
BL set_sfr
|
||||
POP {PC}
|
||||
ENDP
|
||||
|
||||
clear_IRQ_TIM2 PROC
|
||||
EXPORT clear_IRQ_TIM2
|
||||
PUSH {LR}
|
||||
LDR R0, =REG_TIM2_SR
|
||||
LDR R1, =0x1 ; Clear irq pending bit
|
||||
BL clear_sfr
|
||||
POP {PC}
|
||||
ENDP
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -----------------------------------------------------------------------------
|
||||
ALIGN
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
;* ----------------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ----------------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT1 - Lab 12
|
||||
;* -- Description : Common procedures
|
||||
;* --
|
||||
;* -- $Id: utils.s 1244 2015-02-03 10:12:17Z ruan $
|
||||
;* ----------------------------------------------------------------------------
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- Constants
|
||||
; -----------------------------------------------------------------------------
|
||||
|
||||
AREA myCode, CODE, READONLY
|
||||
|
||||
THUMB
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Set bit of a register (SFR, word -> 32 bit)
|
||||
; - Address of register in R6
|
||||
; - Bits to be set in R7
|
||||
; -----------------------------------------------------------------------------
|
||||
set_sfr PROC
|
||||
EXPORT set_sfr
|
||||
|
||||
PUSH {LR}
|
||||
|
||||
LDR R2, [R0] ; Load register value to R0
|
||||
ORRS R2, R2, R1 ; Set bits
|
||||
STR R2, [R0] ; Store new register value
|
||||
|
||||
POP {PC} ; Restore registers and return
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; Clear all bits of a register (SFR, word -> 32 bit)
|
||||
; - Address of register in R0
|
||||
; - Bits to be cleared in R1
|
||||
; -----------------------------------------------------------------------------
|
||||
clear_sfr PROC
|
||||
EXPORT clear_sfr
|
||||
|
||||
PUSH {LR}
|
||||
|
||||
LDR R2, [R0] ; Load register value to R0
|
||||
BICS R2, R2, R1 ; Clear bits
|
||||
STR R2, [R0] ; Store new register value
|
||||
|
||||
POP {PC} ; Restore registers and return
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
; -----------------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -----------------------------------------------------------------------------
|
||||
END
|
||||
|
||||
Loading…
Reference in New Issue