commit cf207b819af52ea1067f692a49223d888b5eb480 Author: Schrom01 Date: Fri Dec 16 15:35:28 2022 +0100 initial commmit diff --git a/CTP_Interrupt.pdf b/CTP_Interrupt.pdf new file mode 100644 index 0000000..c0d4784 Binary files /dev/null and b/CTP_Interrupt.pdf differ diff --git a/code_ASM/Lab.uvoptx b/code_ASM/Lab.uvoptx new file mode 100644 index 0000000..04991c0 --- /dev/null +++ b/code_ASM/Lab.uvoptx @@ -0,0 +1,257 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM)) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + app + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\app\main.s + main.s + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\app\utils.s + utils.s + 0 + 0 + + + 1 + 3 + 2 + 0 + 0 + 0 + .\app\measurement.s + measurement.s + 0 + 0 + + + + + ::Device + 1 + 0 + 0 + 1 + + + + ::HAL + 1 + 0 + 0 + 1 + + + diff --git a/code_ASM/Lab.uvprojx b/code_ASM/Lab.uvprojx new file mode 100644 index 0000000..65d1330 --- /dev/null +++ b/code_ASM/Lab.uvprojx @@ -0,0 +1,529 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6180000::V6.18::ARMCLANG + 6180000::V6.18::ARMCLANG + 1 + + + CT_Board_HS14_M0 + STMicroelectronics + InES.CTBoard14_DFP.4.0.2 + https://ennis.zhaw.ch/pack/ + IROM(0x08000000,0x200000) IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM)) + 0 + + + + + + + + + + + $$Device:CT_Board_HS14_M0$SVD\STM32F429x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + Lab + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + --diag_suppress 6314 + + + + + + + + app + + + main.s + 2 + .\app\main.s + + + utils.s + 2 + .\app\utils.s + + + measurement.s + 2 + .\app\measurement.s + + + + + ::Device + + + ::HAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s + + + + + + + + RTE\Device\CT_Board_HS14_M0\startup_ctboard.s + + + + + + + + RTE\Device\CT_Board_HS14_M0\system_ctboard.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_fmc.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_gpio.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_pwr.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_rcc.c + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/code_ASM/app/analog.s b/code_ASM/app/analog.s new file mode 100644 index 0000000..b4f7d8c --- /dev/null +++ b/code_ASM/app/analog.s @@ -0,0 +1,201 @@ +;* ---------------------------------------------------------------------------- +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ---------------------------------------------------------------------------- +;* -- +;* -- Project : CT1 - Lab 12 +;* -- Description : Read potentiometer and generate analog voltage +;* -- +;* -- 1) Setup ADC for reading analog voltage of potentiometer +;* -- 2) Setup DAC for generating analog voltage signal +;* -- +;* -- $Id: analog.s 1016 2014-11-28 07:27:21Z feur $ +;* ---------------------------------------------------------------------------- + + IMPORT set_sfr + IMPORT clear_sfr + + +; ----------------------------------------------------------------------------- +; -- Constants +; ----------------------------------------------------------------------------- + + AREA myCode, CODE, READONLY + + THUMB + +REG_RCC_AHB1ENR EQU 0x40023830 +REG_RCC_APB1ENR EQU 0x40023840 +REG_RCC_APB2ENR EQU 0x40023844 + +REG_GPIOA_MODER EQU 0x40020000 +REG_GPIOA_OSPEEDR EQU 0x40020008 +REG_GPIOA_PUPDR EQU 0x4002000c +REG_GPIOF_MODER EQU 0x40021400 + +REG_ADC3_SR EQU 0x40012200 +REG_ADC3_CR1 EQU 0x40012204 +REG_ADC3_CR2 EQU 0x40012208 +REG_ADC3_SMPR2 EQU 0x40012210 +REG_ADC3_SQR1 EQU 0x4001222c +REG_ADC3_SQR3 EQU 0x40012234 +REG_ADC3_DR EQU 0x4001224c + +REG_DAC_CR EQU 0x40007400 +REG_DAC_DHR8R1 EQU 0x40007410 + +REG_EXTI_IMR EQU 0x40013c00 +REG_EXTI_RTSR EQU 0x40013c08 +REG_EXTI_FTSR EQU 0x40013c0c + +REG_NVIC_ISER0 EQU 0xe000e100 +REG_NVIC_ICER0 EQU 0xe000e180 + + +; ----------------------------------------------------------------------------- +; Initialize ADC and DAC +; ----------------------------------------------------------------------------- +init_analog PROC + EXPORT init_analog + + PUSH {R6-R7, LR} + +init_adc ; Clock configuration + LDR R6, =REG_RCC_AHB1ENR + LDR R7, =0x20 ; Enable GPIOF clock + BL set_sfr + + LDR R6, =REG_RCC_APB2ENR + LDR R7, =0x400 ; Enable ADC3 clock + BL set_sfr + + ; Analog pin configuration (PF.6) + LDR R6, =REG_GPIOF_MODER + LDR R7, =0x3000 + BL set_sfr + + ; ADC configuration + LDR R6, =REG_ADC3_CR1 + LDR R7, =0x2000000 ; 8 bit resolution + ; Disable scan mode + BL set_sfr + + LDR R6, =REG_ADC3_CR2 + LDR R7, =0x3 ; Enable continous conv. mode + ; Enable ADC + BL set_sfr + + ; Select channel to read from + LDR R6, =REG_ADC3_SMPR2 + LDR R7, =0x6000 ; ch4: 144 cycles sampling time + BL set_sfr + + LDR R6, =REG_ADC3_SQR3 + LDR R7, =0x4 ; ch4: rank 1 (?) + BL set_sfr + + +init_dac ; Clock configuration + LDR R6, =REG_RCC_AHB1ENR + LDR R7, =0x1 ; Enable GPIOA clock + BL set_sfr + + LDR R6, =REG_RCC_APB1ENR + LDR R7, =0x20000000 ; Enable DAC clock + BL set_sfr + + ; Analog pin configuration (PA.4) + LDR R6, =REG_GPIOA_MODER + LDR R7, =0x300 + BL set_sfr + + ; DAC configuration + LDR R6, =REG_DAC_CR + LDR R7, =0x1 ; Enable ch. 1 + BL set_sfr + + LDR R6, =REG_DAC_DHR8R1 + LDR R7, =0x0 ; Set initial value (=0) + BL set_sfr + + ; Return + POP {R6-R7, PC} + + ENDP + + +; ----------------------------------------------------------------------------- +; Process reading ADC and outputing via DAC +; ----------------------------------------------------------------------------- +do_analog PROC + EXPORT do_analog + + PUSH {R0-R2, R6, LR} + + BL get_adc ; Get ADC value in R7 + BL set_dac ; Set DAC value from R7 + + POP {R0-R2, R6, PC} ; Restore registers and return + + ENDP ; Return + + +; ----------------------------------------------------------------------------- +; Convert with ADC an return value +; - converted analog value in R7 +; ----------------------------------------------------------------------------- +get_adc PROC + EXPORT get_adc + + PUSH {R0-R2, R6, LR} + + LDR R6, =REG_ADC3_CR2 + LDR R7, =0x40000000 ; Start conversion + BL set_sfr + + LDR R0, =REG_ADC3_SR +adc_wait LDR R1, =0x2 + LDR R2, [R0] + BICS R1, R1, R2 ; Is conversion finished + BNE adc_wait + + LDR R0, =REG_ADC3_DR + LDR R1, [R0] ; Get converted value + LDR R7, =0xffff + ANDS R7, R7, R1 ; Mask upper halfword + + POP {R0-R2, R6, PC} ; Restore registers and return + + ENDP ; Return + + +; ----------------------------------------------------------------------------- +; Set DAC output +; - digital value in R7 +; ----------------------------------------------------------------------------- +set_dac PROC + EXPORT set_dac + + PUSH {R0-R1, R6, LR} + + LDR R6, =REG_DAC_DHR8R1 + LDR R0, [R6] + LDR R1, =0xff + BICS R0, R0, R1 ; Clear bits + STR R0, [R6] + BL set_sfr ; Set value in R7 + + POP {R0-R1, R6, PC} ; Restore registers and return + + ENDP ; Return + + +; ----------------------------------------------------------------------------- +; -- End of file +; ----------------------------------------------------------------------------- + END + diff --git a/code_ASM/app/control.s b/code_ASM/app/control.s new file mode 100644 index 0000000..f3703fd --- /dev/null +++ b/code_ASM/app/control.s @@ -0,0 +1,165 @@ +;* ---------------------------------------------------------------------------- +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ---------------------------------------------------------------------------- +;* -- +;* -- Project : CT1 - Lab 12 +;* -- Description : Control motor speed and direction +;* -- +;* -- $Id: control.s 1016 2014-11-28 07:27:21Z feur $ +;* ---------------------------------------------------------------------------- + + IMPORT set_sfr + IMPORT clear_sfr + + +; ----------------------------------------------------------------------------- +; -- Constants +; ----------------------------------------------------------------------------- + + AREA myCode, CODE, READONLY + + THUMB + +REG_RCC_AHB1ENR EQU 0x40023830 + +REG_GPIOA_MODER EQU 0x40020000 +REG_GPIOA_OSPEEDR EQU 0x40020008 +REG_GPIOA_BSRR EQU 0x40020018 + +REG_CT_DIPSW EQU 0x60000200 + +jump_table DCD case_00, case_01, case_10, case_11 + +; ----------------------------------------------------------------------------- +; Initialize EXTI +; ----------------------------------------------------------------------------- +init_control PROC + EXPORT init_control + + PUSH {R6-R7, LR} + +init_gpio ; Clock configuration + LDR R6, =REG_RCC_AHB1ENR + LDR R7, =0x1 ; Enable GPIOA clock + BL set_sfr + + ; Output pin configuration (PA.5, PA.6) + LDR R6, =REG_GPIOA_MODER + LDR R7, =0x1400 ; Set pin to output mode + BL set_sfr + + LDR R6, =REG_GPIOA_OSPEEDR + LDR R7, =0x1400 ; Set pin to high speed + BL set_sfr + + ; Return + POP {R6-R7, PC} + + NOP + ENDP + + +; ----------------------------------------------------------------------------- +; Check buttons +; ----------------------------------------------------------------------------- +do_input PROC + EXPORT do_input + + PUSH {R0-R2, LR} + + LDR R0, =REG_CT_DIPSW + LDRB R1, [R0] + LDR R2, =0x3 + ANDS R1, R1, R2 + +case_switch CMP R1, #4 + BGE case_00 + LSLS R1, #2 + LDR R2, =jump_table + LDR R2, [R2, R1] + BX R2 + +case_00 BL motor_off + BL motor_ccw + B case_end + +case_01 BL motor_on + BL motor_ccw + B case_end + +case_10 BL motor_off + BL motor_cw + B case_end + +case_11 BL motor_on + BL motor_cw + +case_end POP {R0-R2, PC} + ENDP + + +; ----------------------------------------------------------------------------- +; Motor control +; ----------------------------------------------------------------------------- +motor_on PROC + EXPORT motor_on + + PUSH {R0-R7, LR} + + LDR R0, =REG_GPIOA_BSRR + LDR R1, =0x20 ; Set bit 5 -> PA.5 + STR R1, [R0] + + POP {R0-R7, PC} + ENDP + + +motor_off PROC + EXPORT motor_off + + PUSH {R0-R7, LR} + + LDR R0, =REG_GPIOA_BSRR + LDR R1, =0x200000 ; Reset bit 5 -> PA.5 + STR R1, [R0] + + POP {R0-R7, PC} + ENDP + + +motor_cw PROC + EXPORT motor_cw + + PUSH {R0-R7, LR} + + LDR R0, =REG_GPIOA_BSRR + LDR R1, =0x40 ; Set bit 6 -> PA.6 + STR R1, [R0] + + POP {R0-R7, PC} + ENDP + + +motor_ccw PROC + EXPORT motor_ccw + + PUSH {R0-R7, LR} + + LDR R0, =REG_GPIOA_BSRR + LDR R1, =0x400000 ; Reset bit 6 -> PA.6 + STR R1, [R0] + + POP {R0-R7, PC} + ENDP + + +; ----------------------------------------------------------------------------- +; -- End of file +; ----------------------------------------------------------------------------- + END + diff --git a/code_ASM/app/main.s b/code_ASM/app/main.s new file mode 100644 index 0000000..904f0e2 --- /dev/null +++ b/code_ASM/app/main.s @@ -0,0 +1,104 @@ +;* ---------------------------------------------------------------------------- +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ---------------------------------------------------------------------------- +;* -- +;* -- Project : CT1 - Lab 12 +;* -- Description : Reading the User-Button as Interrupt source +;* -- +;* -- $Id: main.s 5082 2020-05-14 13:56:07Z akdi $ +;* -- +;* ---------------------------------------------------------------------------- + + + IMPORT init_measurement + IMPORT clear_IRQ_EXTI0 + IMPORT clear_IRQ_TIM2 + +; ----------------------------------------------------------------------------- +; -- Constants +; ----------------------------------------------------------------------------- + + AREA myCode, CODE, READONLY + + THUMB + +REG_GPIOA_IDR EQU 0x40020010 +LED_15_0 EQU 0x60000100 +LED_16_31 EQU 0x60000102 +REG_CT_7SEG EQU 0x60000114 +REG_SETENA0 EQU 0xe000e100 + + +; ----------------------------------------------------------------------------- +; -- Main +; ----------------------------------------------------------------------------- +main PROC + EXPORT main + + + BL init_measurement + + ; Configure NVIC (enable interrupt channel) + ; STUDENTS: To be programmed + + + ; END: To be programmed + + ; Initialize variables + ; STUDENTS: To be programmed + + + ; END: To be programmed + +loop + ; Output counter on 7-seg + ; STUDENTS: To be programmed + + + ; END: To be programmed + + B loop + + + ENDP + + +; ----------------------------------------------------------------------------- +; Handler for EXTI0 interrupt +; ----------------------------------------------------------------------------- + ; STUDENTS: To be programmed + + + ; END: To be programmed + + +; ----------------------------------------------------------------------------- +; Handler for TIM2 interrupt +; ----------------------------------------------------------------------------- + ; STUDENTS: To be programmed + + + ; END: To be programmed + ALIGN + +; ----------------------------------------------------------------------------- +; -- Variables +; ----------------------------------------------------------------------------- + + AREA myVars, DATA, READWRITE + + ; STUDENTS: To be programmed + + + ; END: To be programmed + + +; ----------------------------------------------------------------------------- +; -- End of file +; ----------------------------------------------------------------------------- + END diff --git a/code_ASM/app/measurement.s b/code_ASM/app/measurement.s new file mode 100644 index 0000000..c3469f1 --- /dev/null +++ b/code_ASM/app/measurement.s @@ -0,0 +1,138 @@ +;* ---------------------------------------------------------------------------- +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ---------------------------------------------------------------------------- +;* -- +;* -- Project : CT1 - Lab 12 +;* -- Description : Meassuring motor speed and direction +;* -- +;* -- 1) Setup external interrupt EXTI for counting motor pulses +;* -- 2) Setup TIM2 for generating 1 Hz reference clock +;* -- 3) Functions to clear IRQ Flip-flops +;* -- +;* -- $Id: measurement.s 3858 2017-01-09 13:26:26Z kesr $ +;* ---------------------------------------------------------------------------- + + IMPORT set_sfr + IMPORT clear_sfr + + +; ----------------------------------------------------------------------------- +; -- Constants +; ----------------------------------------------------------------------------- + + AREA myCode, CODE, READONLY + + THUMB + +REG_RCC_AHB1ENR EQU 0x40023830 +REG_RCC_APB1ENR EQU 0x40023840 +REG_RCC_APB2ENR EQU 0x40023844 + +REG_GPIOA_PUPDR EQU 0x4002000c + +REG_EXTI_IMR EQU 0x40013c00 +REG_EXTI_RTSR EQU 0x40013c08 +REG_EXTI_PR EQU 0x40013c14 + +REG_TIM2_CR1 EQU 0x40000000 +REG_TIM2_DIER EQU 0x4000000c +REG_TIM2_SR EQU 0x40000010 +REG_TIM2_EGR EQU 0x40000014 +REG_TIM2_PSC EQU 0x40000028 +REG_TIM2_ARR EQU 0x4000002c + + + +; ----------------------------------------------------------------------------- +; Initialize EXTI +; ----------------------------------------------------------------------------- +init_measurement PROC + EXPORT init_measurement + + PUSH {LR} + +init_exti ; Clock configuration + LDR R0, =REG_RCC_AHB1ENR + LDR R1, =0x1 ; Enable GPIOA clock + BL set_sfr + + LDR R0, =REG_RCC_APB2ENR + LDR R1, =0x4000 ; Enable SYSCFG clock + BL set_sfr + + ; Input pin configuration (PA.0) + LDR R0, =REG_GPIOA_PUPDR + LDR R1, =0x2 ; Set pin to pull-down mode + BL set_sfr + + ; Configure EXTI + LDR R0, =REG_EXTI_IMR + LDR R1, =0x1 ; Unmask EXTI0 interrupt + BL set_sfr + + LDR R0, =REG_EXTI_RTSR + LDR R1, =0x1 ; Trigger on rising edge + BL set_sfr + + +init_timer ; Clock configuration + LDR R0, =REG_RCC_APB1ENR + LDR R1, =0x1 ; Enable TIM2 clock + BL set_sfr + + ; Configure TIM2 frequency + LDR R0, =REG_TIM2_PSC + LDR R1, =839 ; Timer prescaler => 84Mhz / 840 = 100kHz => 10us + BL set_sfr + + LDR R0, =REG_TIM2_ARR + LDR R1, =0xffffffff ; Clear Register first, it gets + BL clear_sfr ; initialized with 0xffffffff + LDR R1, =199998 ; Autoreload value => 99999+1 => 1s + BL set_sfr + + LDR R0, =REG_TIM2_EGR + LDR R1, =0x1 ; Update TIM2 configuration + BL set_sfr + + LDR R0, =REG_TIM2_DIER + LDR R1, =0x1 ; Enable interrupt source + BL set_sfr + + LDR R0, =REG_TIM2_CR1 + LDR R1, =0x1 ; Enable TIM2 + BL set_sfr + + ; Return + POP {PC} + ENDP + +clear_IRQ_EXTI0 PROC + EXPORT clear_IRQ_EXTI0 + PUSH {LR} + LDR R0, =REG_EXTI_PR + LDR R1, =0x1 ; Clear irq pending bit + BL set_sfr + POP {PC} + ENDP + +clear_IRQ_TIM2 PROC + EXPORT clear_IRQ_TIM2 + PUSH {LR} + LDR R0, =REG_TIM2_SR + LDR R1, =0x1 ; Clear irq pending bit + BL clear_sfr + POP {PC} + ENDP + +; ----------------------------------------------------------------------------- +; -- End of file +; ----------------------------------------------------------------------------- + ALIGN + END + diff --git a/code_ASM/app/utils.s b/code_ASM/app/utils.s new file mode 100644 index 0000000..2019069 --- /dev/null +++ b/code_ASM/app/utils.s @@ -0,0 +1,68 @@ +;* ---------------------------------------------------------------------------- +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ---------------------------------------------------------------------------- +;* -- +;* -- Project : CT1 - Lab 12 +;* -- Description : Common procedures +;* -- +;* -- $Id: utils.s 1244 2015-02-03 10:12:17Z ruan $ +;* ---------------------------------------------------------------------------- + + +; ----------------------------------------------------------------------------- +; -- Constants +; ----------------------------------------------------------------------------- + + AREA myCode, CODE, READONLY + + THUMB + + +; ----------------------------------------------------------------------------- +; Set bit of a register (SFR, word -> 32 bit) +; - Address of register in R6 +; - Bits to be set in R7 +; ----------------------------------------------------------------------------- +set_sfr PROC + EXPORT set_sfr + + PUSH {LR} + + LDR R2, [R0] ; Load register value to R0 + ORRS R2, R2, R1 ; Set bits + STR R2, [R0] ; Store new register value + + POP {PC} ; Restore registers and return + + ENDP + + +; ----------------------------------------------------------------------------- +; Clear all bits of a register (SFR, word -> 32 bit) +; - Address of register in R0 +; - Bits to be cleared in R1 +; ----------------------------------------------------------------------------- +clear_sfr PROC + EXPORT clear_sfr + + PUSH {LR} + + LDR R2, [R0] ; Load register value to R0 + BICS R2, R2, R1 ; Clear bits + STR R2, [R0] ; Store new register value + + POP {PC} ; Restore registers and return + + ENDP + + +; ----------------------------------------------------------------------------- +; -- End of file +; ----------------------------------------------------------------------------- + END +