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CT_Lab_2_BitManipulations
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solved Task 3.1

This commit is contained in:
Schrom01 2022-09-30 08:35:44 +02:00
parent bbad8751ee
commit 63e84bd4ec
66 changed files with 17409 additions and 4 deletions
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>6</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U48FF68066765565148400667 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::HAL</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>CT_Board_HS14_M0</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>InES.CTBoard14_DFP.4.0.2</PackID>
<PackURL>https://ennis.zhaw.ch/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:CT_Board_HS14_M0$SVD\STM32F429x.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>CT-Lab2-Project</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP-MPU </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x30000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x200000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x30000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--diag_suppress 6314</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
<Group>
<GroupName>::HAL</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0">
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
<component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL">
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
<component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL">
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
<component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL">
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
<component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL">
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="Device\Source\datainit_ctboard.s" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\startup_ctboard.s" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\startup_ctboard.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\system_ctboard.c" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\system_ctboard.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="HAL\Source\hal_fmc.c" version="3.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_fmc.c</instance>
<component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="HAL\Source\hal_gpio.c" version="4.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_gpio.c</instance>
<component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="HAL\Source\hal_pwr.c" version="2.2.0">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_pwr.c</instance>
<component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
<file attr="config" category="source" name="HAL\Source\hal_rcc.c" version="4.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_rcc.c</instance>
<component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>

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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

439
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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

132
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

347
CT-Lab2-TestProject/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

143
CT-Lab2-TestProject/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

412
CT-Lab2-TestProject/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

132
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

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CT-Lab2-TestProject/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

15
CT-Lab2-TestProject/RTE/_Target_1/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'CT-Lab2-Project'
* Target: 'Target 1'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */

0
CT-Lab2-TestProject/main.c Normal file
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9
bit_manipulations/EventRecorderStub.scvd Normal file
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

100
bit_manipulations/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 Normal file
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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

439
bit_manipulations/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 Normal file
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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

290
bit_manipulations/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

100
bit_manipulations/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s Normal file
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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

439
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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

143
bit_manipulations/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

412
bit_manipulations/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

132
bit_manipulations/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

347
bit_manipulations/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

347
bit_manipulations/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c Normal file
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@ -0,0 +1,347 @@
/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

15
bit_manipulations/RTE/_Target_1/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'bitmanipulation'
* Target: 'Target 1'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */

6
bit_manipulations/app/main.c
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@ -27,7 +27,8 @@
// define your own macros for bitmasks below (#define)
/// STUDENTS: To be programmed
#define BRIGHT_MASK 0xC0
#define DARK_MASK 0xCF
@ -50,7 +51,8 @@ int main(void)
led_value = read_byte(ADDR_DIP_SWITCH_7_0);
/// STUDENTS: To be programmed
led_value = (led_value | BRIGHT_MASK);
led_value = (led_value & DARK_MASK);

3637
bit_manipulations/bitmanipulation.uvguix.roman Normal file
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File diff suppressed because one or more lines are too long

24
bit_manipulations/bitmanipulation.uvoptx
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@ -117,6 +117,26 @@
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
@ -135,12 +155,12 @@
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>

2
bit_manipulations/build/ExtDll.iex Normal file
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[EXTDLL]
Count=0

BIN
bit_manipulations/build/bitmanipulation.axf Normal file
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Binary file not shown.

98
bit_manipulations/build/bitmanipulation.build_log.htm Normal file
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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.37.0.0
Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Roman Schenk, ZHAW, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.37.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCLANG\Bin
C Compiler: ArmClang.exe V6.18
Assembler: Armasm.exe V6.18
Linker/Locator: ArmLink.exe V6.18
Library Manager: ArmAr.exe V6.18
Hex Converter: FromElf.exe V6.18
CPU DLL: SARMCM3.DLL V5.37.0.0
Dialog DLL: DARMCM1.DLL V1.19.6.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.9.0
Dialog DLL: TARMCM1.DLL V1.14.6.0
<h2>Project:</h2>
C:\Users\roman\Documents\Lab_2_BitManipulations\bit_manipulations\bitmanipulation.uvprojx
Project File Date: 09/30/2022
<h2>Output:</h2>
*** Using Compiler 'V6.18', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
Rebuild target 'Target 1'
assembling startup_ctboard.s...
assembling datainit_ctboard.s...
compiling utils_ctboard.c...
compiling main.c...
compiling system_ctboard.c...
compiling hal_fmc.c...
compiling hal_pwr.c...
compiling hal_gpio.c...
compiling hal_rcc.c...
linking...
Program Size: Code=3456 RO-data=428 RW-data=0 ZI-data=8192
".\build\bitmanipulation.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: InES
https://ennis.zhaw.ch/pack/InES.CTBoard14_DFP.4.0.2.pack
InES.CTBoard14_DFP.4.0.2
CT Board 14 (STM32F429ZI) Device Support
* Component: Startup Version: 4.0.1
* Component: FMC Version: 3.0.1
* Component: GPIO Version: 4.0.1
* Component: PWR Version: 2.2.0
* Component: RCC Version: 4.0.1
<h2>Collection of Component include folders:</h2>
./RTE/_Target_1
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
<h2>Collection of Component Files used:</h2>
* Component: InES::Device:Startup:4.0.1
Include file: Device/Include/m0/platform_ctboard.h
Include file: Device/Include/reg_stm32f4xx.h
Include file: Device/Include/reg_ctboard.h
Source file: Device/Source/system_ctboard.c
Source file: Device/Source/startup_ctboard.s
Source file: Device/Source/datainit_ctboard.s
Include file: Device/Include/system_ctboard.h
* Component: InES::HAL:FMC:3.0.1
Include file: HAL/Include/hal_common.h
Source file: HAL/Source/hal_fmc.c
Include file: HAL/Include/hal_fmc.h
Include file: Device/Include/reg_stm32f4xx.h
* Component: InES::HAL:GPIO:4.0.1
Include file: HAL/Include/hal_common.h
Include file: HAL/Include/hal_gpio.h
Source file: HAL/Source/hal_gpio.c
Include file: Device/Include/reg_stm32f4xx.h
* Component: InES::HAL:PWR:2.2.0
Include file: HAL/Include/hal_common.h
Source file: HAL/Source/hal_pwr.c
Include file: HAL/Include/hal_pwr.h
Include file: Device/Include/reg_stm32f4xx.h
* Component: InES::HAL:RCC:4.0.1
Include file: HAL/Include/hal_common.h
Include file: Device/Include/reg_stm32f4xx.h
Include file: HAL/Include/hal_rcc.h
Source file: HAL/Source/hal_rcc.c
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>

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bit_manipulations/build/bitmanipulation.htm Normal file
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [.\build\bitmanipulation.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\build\bitmanipulation.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 6180002: Last Updated: Fri Sep 30 08:34:36 2022
<BR><P>
<H3>Maximum Stack Usage = 132 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
__system &rArr; system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
<LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
<LI><a href="#[3]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">MemManage_Handler</a><BR>
<LI><a href="#[4]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">BusFault_Handler</a><BR>
<LI><a href="#[5]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">UsageFault_Handler</a><BR>
<LI><a href="#[6]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[6]">SVC_Handler</a><BR>
<LI><a href="#[7]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[7]">DebugMon_Handler</a><BR>
<LI><a href="#[8]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[8]">PendSV_Handler</a><BR>
<LI><a href="#[9]">SysTick_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[9]">SysTick_Handler</a><BR>
<LI><a href="#[1c]">ADC_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC_IRQHandler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[1c]">ADC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4]">BusFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1e]">CAN1_RX0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1d]">CAN1_TX_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4a]">CAN2_RX0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4b]">CAN2_RX1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4c]">CAN2_SCE_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[49]">CAN2_TX_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[59]">CRYP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[58]">DCMI_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[15]">DMA1_Stream0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[16]">DMA1_Stream1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[17]">DMA1_Stream2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[18]">DMA1_Stream3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[19]">DMA1_Stream4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1a]">DMA1_Stream5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1b]">DMA1_Stream6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[39]">DMA1_Stream7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[64]">DMA2D_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[42]">DMA2_Stream0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[43]">DMA2_Stream1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[44]">DMA2_Stream2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[45]">DMA2_Stream3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[46]">DMA2_Stream4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4e]">DMA2_Stream5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4f]">DMA2_Stream6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[50]">DMA2_Stream7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[7]">DebugMon_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[47]">ETH_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[48]">ETH_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[e]">FLASH_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3a]">FMC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5b]">FPU_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5a]">HASH_RNG_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2]">HardFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[53]">I2C3_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[52]">I2C3_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[63]">LTDC_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[62]">LTDC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3]">MemManage_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1]">NMI_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4d]">OTG_FS_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[34]">OTG_FS_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[55]">OTG_HS_EP1_IN_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[54]">OTG_HS_EP1_OUT_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[57]">OTG_HS_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[56]">OTG_HS_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[b]">PVD_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[8]">PendSV_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[f]">RCC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[d]">RTC_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[0]">Reset_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[61]">SAI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3b]">SDIO_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3d]">SPI3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5e]">SPI4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5f]">SPI5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[60]">SPI6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[6]">SVC_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[9]">SysTick_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[c]">TAMP_STAMP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[22]">TIM1_BRK_TIM9_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[25]">TIM1_CC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[24]">TIM1_TRG_COM_TIM11_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[23]">TIM1_UP_TIM10_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[26]">TIM2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[27]">TIM3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[28]">TIM4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3c]">TIM5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[40]">TIM6_DAC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[41]">TIM7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[35]">TIM8_BRK_TIM12_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[38]">TIM8_CC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[37]">TIM8_TRG_COM_TIM14_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[36]">TIM8_UP_TIM13_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3e]">UART4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3f]">UART5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5c]">UART7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5d]">UART8_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2f]">USART1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[30]">USART2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[31]">USART3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[51]">USART6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5]">UsageFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[a]">WWDG_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[67]">__main</a> from datainit_ctboard.o(.text) referenced from startup_ctboard.o(.text)
<LI><a href="#[66]">__system</a> from system_ctboard.o(.text) referenced from startup_ctboard.o(.text)
<LI><a href="#[65]">main</a> from main.o(.text) referenced from datainit_ctboard.o(.text)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[65]"></a>main</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, main.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;write_byte
<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;read_byte
</UL>
<BR>[Address Reference Count : 1]<UL><LI> datainit_ctboard.o(.text)
</UL>
<P><STRONG><a name="[68]"></a>read_byte</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[73]"></a>read_halfword</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[74]"></a>read_word</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[75]"></a>read_doubleword</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[69]"></a>write_byte</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[76]"></a>write_halfword</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[77]"></a>write_word</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[78]"></a>write_doubleword</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, utils_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[67]"></a>__main</STRONG> (Thumb, 74 bytes, Stack size 0 bytes, datainit_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(.text)
</UL>
<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4a]"></a>CAN2_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4b]"></a>CAN2_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4c]"></a>CAN2_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[49]"></a>CAN2_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[59]"></a>CRYP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[58]"></a>DCMI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>DMA1_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>DMA1_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>DMA1_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>DMA1_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>DMA1_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>DMA1_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>DMA1_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>DMA1_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[64]"></a>DMA2D_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>DMA2_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[43]"></a>DMA2_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[44]"></a>DMA2_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[45]"></a>DMA2_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[46]"></a>DMA2_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>DMA2_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4f]"></a>DMA2_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[50]"></a>DMA2_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[47]"></a>ETH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[48]"></a>ETH_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3a]"></a>FMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5b]"></a>FPU_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5a]"></a>HASH_RNG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[53]"></a>I2C3_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[52]"></a>I2C3_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[63]"></a>LTDC_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[62]"></a>LTDC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4d]"></a>OTG_FS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>OTG_FS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[55]"></a>OTG_HS_EP1_IN_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[54]"></a>OTG_HS_EP1_OUT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[57]"></a>OTG_HS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[56]"></a>OTG_HS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>RTC_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[61]"></a>SAI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3b]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3d]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5e]"></a>SPI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5f]"></a>SPI5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[60]"></a>SPI6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>TAMP_STAMP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>TIM1_BRK_TIM9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>TIM1_TRG_COM_TIM11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[23]"></a>TIM1_UP_TIM10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3c]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[40]"></a>TIM6_DAC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[35]"></a>TIM8_BRK_TIM12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[38]"></a>TIM8_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[37]"></a>TIM8_TRG_COM_TIM14_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[36]"></a>TIM8_UP_TIM13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3e]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3f]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5c]"></a>UART7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5d]"></a>UART8_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[51]"></a>USART6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[66]"></a>__system</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_ctboard.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 132<LI>Call Chain = __system &rArr; system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(.text)
</UL>
<P><STRONG><a name="[6a]"></a>system_enter_run</STRONG> (Thumb, 280 bytes, Stack size 48 bytes, system_ctboard.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 124<LI>Call Chain = system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_fmc_init_sram
<LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_alternate
<LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_setup_clock
<LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_pwr_set_overdrive
<LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_setup_pll
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_set_osc
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_reset
</UL>
<BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__system
</UL>
<P><STRONG><a name="[79]"></a>system_enter_sleep</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[7a]"></a>system_enter_stop</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[7b]"></a>system_enter_standby</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[7c]"></a>hal_fmc_reset</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, hal_fmc.o(.text), UNUSED)
<P><STRONG><a name="[71]"></a>hal_fmc_init_sram</STRONG> (Thumb, 264 bytes, Stack size 36 bytes, hal_fmc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_fmc_init_sram
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[7d]"></a>hal_gpio_reset</STRONG> (Thumb, 68 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7e]"></a>hal_gpio_init_input</STRONG> (Thumb, 156 bytes, Stack size 32 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7f]"></a>hal_gpio_init_analog</STRONG> (Thumb, 240 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[72]"></a>hal_gpio_init_output</STRONG> (Thumb, 276 bytes, Stack size 36 bytes, hal_gpio.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_gpio_init_output
</UL>
<BR>[Called By]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_alternate
</UL>
<P><STRONG><a name="[70]"></a>hal_gpio_init_alternate</STRONG> (Thumb, 262 bytes, Stack size 40 bytes, hal_gpio.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 76<LI>Call Chain = hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_output
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[80]"></a>hal_gpio_input_read</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[81]"></a>hal_gpio_output_read</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[82]"></a>hal_gpio_output_write</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[83]"></a>hal_gpio_bit_set</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[84]"></a>hal_gpio_bit_reset</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[85]"></a>hal_gpio_bit_toggle</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[86]"></a>hal_gpio_irq_set</STRONG> (Thumb, 292 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[87]"></a>hal_gpio_irq_status</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[88]"></a>hal_gpio_irq_clear</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[89]"></a>hal_pwr_reset</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[8a]"></a>hal_pwr_set_backup_domain</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[8b]"></a>hal_pwr_set_backup_access</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[8c]"></a>hal_pwr_set_wakeup_pin</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[8d]"></a>hal_pwr_set_flash_powerdown</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[6e]"></a>hal_pwr_set_overdrive</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[8e]"></a>hal_pwr_set_underdrive</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[6b]"></a>hal_rcc_reset</STRONG> (Thumb, 104 bytes, Stack size 16 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_rcc_reset
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[8f]"></a>hal_rcc_set_peripheral</STRONG> (Thumb, 228 bytes, Stack size 8 bytes, hal_rcc.o(.text), UNUSED)
<P><STRONG><a name="[6c]"></a>hal_rcc_set_osc</STRONG> (Thumb, 108 bytes, Stack size 16 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_rcc_set_osc
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[6d]"></a>hal_rcc_setup_pll</STRONG> (Thumb, 220 bytes, Stack size 24 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_rcc_setup_pll
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[6f]"></a>hal_rcc_setup_clock</STRONG> (Thumb, 80 bytes, Stack size 16 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_rcc_setup_clock
</UL>
<BR>[Called By]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P>
<H3>
Local Symbols
</H3><P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>

14
bit_manipulations/build/bitmanipulation.lnp Normal file
View File

@ -0,0 +1,14 @@
--cpu Cortex-M0
".\build\main.o"
".\build\utils_ctboard.o"
".\build\datainit_ctboard.o"
".\build\startup_ctboard.o"
".\build\system_ctboard.o"
".\build\hal_fmc.o"
".\build\hal_gpio.o"
".\build\hal_pwr.o"
".\build\hal_rcc.o"
--strict --scatter ".\build\bitmanipulation.sct"
--diag_suppress 6314 --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\build\bitmanipulation.map" -o .\build\bitmanipulation.axf

383
bit_manipulations/build/bitmanipulation.map Normal file
View File

@ -0,0 +1,383 @@
Component: Arm Compiler for Embedded 6.18 Tool: armlink [5e4cc100]
==============================================================================
Section Cross References
main.o(.text) refers to utils_ctboard.o(.text) for read_byte
main.o(.ARM.exidx) refers to main.o(.text) for [Anonymous Symbol]
utils_ctboard.o(.ARM.exidx) refers to utils_ctboard.o(.text) for [Anonymous Symbol]
datainit_ctboard.o(.text) refers (Weak) to startup_ctboard.o(STACK) for Stack_Mem
datainit_ctboard.o(.text) refers to main.o(.text) for main
startup_ctboard.o(RESET) refers to startup_ctboard.o(STACK) for __initial_sp
startup_ctboard.o(RESET) refers to startup_ctboard.o(.text) for Reset_Handler
startup_ctboard.o(.text) refers to system_ctboard.o(.text) for __system
startup_ctboard.o(.text) refers to datainit_ctboard.o(.text) for __main
system_ctboard.o(.text) refers to hal_rcc.o(.text) for hal_rcc_reset
system_ctboard.o(.text) refers to hal_pwr.o(.text) for hal_pwr_set_overdrive
system_ctboard.o(.text) refers to hal_gpio.o(.text) for hal_gpio_init_alternate
system_ctboard.o(.text) refers to hal_fmc.o(.text) for hal_fmc_init_sram
system_ctboard.o(.ARM.exidx) refers to system_ctboard.o(.text) for [Anonymous Symbol]
hal_fmc.o(.ARM.exidx) refers to hal_fmc.o(.text) for [Anonymous Symbol]
hal_gpio.o(.ARM.exidx) refers to hal_gpio.o(.text) for [Anonymous Symbol]
hal_pwr.o(.ARM.exidx) refers to hal_pwr.o(.text) for [Anonymous Symbol]
hal_rcc.o(.ARM.exidx) refers to hal_rcc.o(.text) for [Anonymous Symbol]
==============================================================================
Removing Unused input sections from the image.
Removing main.o(.ARM.exidx), (8 bytes).
Removing main.o(.ARM.use_no_argv), (4 bytes).
Removing utils_ctboard.o(.ARM.exidx), (64 bytes).
Removing startup_ctboard.o(HEAP), (2048 bytes).
Removing system_ctboard.o(.ARM.exidx), (40 bytes).
Removing hal_fmc.o(.ARM.exidx), (16 bytes).
Removing hal_gpio.o(.ARM.exidx), (112 bytes).
Removing hal_pwr.o(.ARM.exidx), (56 bytes).
Removing hal_rcc.o(.ARM.exidx), (40 bytes).
9 unused section(s) (total 2388 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s 0x00000000 Number 0 datainit_ctboard.o ABSOLUTE
RTE/Device/CT_Board_HS14_M0/startup_ctboard.s 0x00000000 Number 0 startup_ctboard.o ABSOLUTE
hal_fmc.c 0x00000000 Number 0 hal_fmc.o ABSOLUTE
hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE
hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE
hal_rcc.c 0x00000000 Number 0 hal_rcc.o ABSOLUTE
main.c 0x00000000 Number 0 main.o ABSOLUTE
system_ctboard.c 0x00000000 Number 0 system_ctboard.o ABSOLUTE
utils_ctboard.c 0x00000000 Number 0 utils_ctboard.o ABSOLUTE
RESET 0x08000000 Section 428 startup_ctboard.o(RESET)
[Anonymous Symbol] 0x080001ac Section 0 main.o(.text)
__arm_cp.0_0 0x080001c8 Number 4 main.o(.text)
__arm_cp.0_1 0x080001cc Number 4 main.o(.text)
[Anonymous Symbol] 0x080001d0 Section 0 utils_ctboard.o(.text)
.text 0x080001f4 Section 124 datainit_ctboard.o(.text)
.text 0x08000270 Section 36 startup_ctboard.o(.text)
[Anonymous Symbol] 0x08000294 Section 0 system_ctboard.o(.text)
__arm_cp.1_0 0x080003b4 Number 4 system_ctboard.o(.text)
__arm_cp.1_1 0x080003b8 Number 4 system_ctboard.o(.text)
__arm_cp.1_2 0x080003bc Number 4 system_ctboard.o(.text)
__arm_cp.1_3 0x080003c0 Number 4 system_ctboard.o(.text)
__arm_cp.1_4 0x080003c4 Number 4 system_ctboard.o(.text)
__arm_cp.1_5 0x080003c8 Number 4 system_ctboard.o(.text)
__arm_cp.1_6 0x080003cc Number 4 system_ctboard.o(.text)
__arm_cp.1_7 0x080003d0 Number 4 system_ctboard.o(.text)
__arm_cp.1_8 0x080003d4 Number 4 system_ctboard.o(.text)
__arm_cp.1_9 0x080003d8 Number 4 system_ctboard.o(.text)
__arm_cp.1_10 0x080003dc Number 4 system_ctboard.o(.text)
__arm_cp.1_11 0x080003e0 Number 4 system_ctboard.o(.text)
__arm_cp.1_12 0x080003e4 Number 4 system_ctboard.o(.text)
__arm_cp.1_13 0x080003e8 Number 4 system_ctboard.o(.text)
__arm_cp.1_14 0x080003ec Number 4 system_ctboard.o(.text)
[Anonymous Symbol] 0x080003f8 Section 0 hal_fmc.o(.text)
__arm_cp.0_0 0x08000434 Number 4 hal_fmc.o(.text)
__arm_cp.0_1 0x08000438 Number 4 hal_fmc.o(.text)
__arm_cp.0_2 0x0800043c Number 4 hal_fmc.o(.text)
__arm_cp.1_0 0x08000548 Number 4 hal_fmc.o(.text)
[Anonymous Symbol] 0x0800054c Section 0 hal_gpio.o(.text)
__arm_cp.0_0 0x08000590 Number 4 hal_gpio.o(.text)
__arm_cp.0_1 0x08000594 Number 4 hal_gpio.o(.text)
__arm_cp.1_0 0x08000634 Number 4 hal_gpio.o(.text)
__arm_cp.1_1 0x08000638 Number 4 hal_gpio.o(.text)
__arm_cp.2_0 0x0800072c Number 4 hal_gpio.o(.text)
__arm_cp.2_1 0x08000730 Number 4 hal_gpio.o(.text)
__arm_cp.3_0 0x08000848 Number 4 hal_gpio.o(.text)
__arm_cp.3_1 0x0800084c Number 4 hal_gpio.o(.text)
__arm_cp.7_0 0x08000978 Number 4 hal_gpio.o(.text)
__arm_cp.7_1 0x0800097c Number 4 hal_gpio.o(.text)
__arm_cp.8_0 0x08000998 Number 4 hal_gpio.o(.text)
__arm_cp.8_1 0x0800099c Number 4 hal_gpio.o(.text)
__arm_cp.9_0 0x080009bc Number 4 hal_gpio.o(.text)
__arm_cp.9_1 0x080009c0 Number 4 hal_gpio.o(.text)
__arm_cp.10_0 0x080009e0 Number 4 hal_gpio.o(.text)
__arm_cp.10_1 0x080009e4 Number 4 hal_gpio.o(.text)
__arm_cp.11_0 0x08000b0c Number 4 hal_gpio.o(.text)
__arm_cp.11_1 0x08000b10 Number 4 hal_gpio.o(.text)
__arm_cp.11_2 0x08000b14 Number 4 hal_gpio.o(.text)
__arm_cp.11_3 0x08000b18 Number 4 hal_gpio.o(.text)
__arm_cp.11_4 0x08000b1c Number 4 hal_gpio.o(.text)
__arm_cp.11_5 0x08000b20 Number 4 hal_gpio.o(.text)
__arm_cp.12_0 0x08000b3c Number 4 hal_gpio.o(.text)
__arm_cp.13_0 0x08000b4c Number 4 hal_gpio.o(.text)
[Anonymous Symbol] 0x08000b50 Section 0 hal_pwr.o(.text)
__arm_cp.0_0 0x08000b60 Number 4 hal_pwr.o(.text)
__arm_cp.1_0 0x08000b9c Number 4 hal_pwr.o(.text)
__arm_cp.2_0 0x08000bb8 Number 4 hal_pwr.o(.text)
__arm_cp.3_0 0x08000bd4 Number 4 hal_pwr.o(.text)
__arm_cp.4_0 0x08000bf0 Number 4 hal_pwr.o(.text)
[Anonymous Symbol] 0x08000bfc Section 0 hal_rcc.o(.text)
__arm_cp.0_0 0x08000c64 Number 4 hal_rcc.o(.text)
__arm_cp.0_1 0x08000c68 Number 4 hal_rcc.o(.text)
__arm_cp.0_2 0x08000c6c Number 4 hal_rcc.o(.text)
__arm_cp.0_3 0x08000c70 Number 4 hal_rcc.o(.text)
__arm_cp.0_4 0x08000c74 Number 4 hal_rcc.o(.text)
__arm_cp.0_5 0x08000c78 Number 4 hal_rcc.o(.text)
__arm_cp.0_6 0x08000c7c Number 4 hal_rcc.o(.text)
__arm_cp.0_7 0x08000c80 Number 4 hal_rcc.o(.text)
__arm_cp.1_0 0x08000d68 Number 4 hal_rcc.o(.text)
__arm_cp.2_0 0x08000dd8 Number 4 hal_rcc.o(.text)
__arm_cp.2_1 0x08000ddc Number 4 hal_rcc.o(.text)
__arm_cp.3_0 0x08000ebc Number 4 hal_rcc.o(.text)
__arm_cp.3_1 0x08000ec0 Number 4 hal_rcc.o(.text)
__arm_cp.3_2 0x08000ec4 Number 4 hal_rcc.o(.text)
__arm_cp.3_3 0x08000ec8 Number 4 hal_rcc.o(.text)
__arm_cp.3_4 0x08000ecc Number 4 hal_rcc.o(.text)
__arm_cp.3_5 0x08000ed0 Number 4 hal_rcc.o(.text)
__arm_cp.4_0 0x08000f24 Number 4 hal_rcc.o(.text)
__arm_cp.4_1 0x08000f28 Number 4 hal_rcc.o(.text)
STACK 0x20000000 Section 8192 startup_ctboard.o(STACK)
__initial_sp 0x20002000 Data 0 startup_ctboard.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$WCHAR32$ENUMINT$~SHL$OTIME$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
Image$$RO$$Limit - Undefined Weak Reference
Image$$RW$$Base - Undefined Weak Reference
Image$$ZI$$Base - Undefined Weak Reference
Image$$ZI$$Limit - Undefined Weak Reference
__Vectors_Size 0x000001ac Number 0 startup_ctboard.o ABSOLUTE
Stack_Size 0x00002000 Number 0 startup_ctboard.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_ctboard.o(RESET)
__Vectors_End 0x080001ac Data 0 startup_ctboard.o(RESET)
main 0x080001ad Thumb Code 28 main.o(.text)
read_byte 0x080001d1 Thumb Code 4 utils_ctboard.o(.text)
read_halfword 0x080001d5 Thumb Code 4 utils_ctboard.o(.text)
read_word 0x080001d9 Thumb Code 4 utils_ctboard.o(.text)
read_doubleword 0x080001dd Thumb Code 8 utils_ctboard.o(.text)
write_byte 0x080001e5 Thumb Code 4 utils_ctboard.o(.text)
write_halfword 0x080001e9 Thumb Code 4 utils_ctboard.o(.text)
write_word 0x080001ed Thumb Code 4 utils_ctboard.o(.text)
write_doubleword 0x080001f1 Thumb Code 4 utils_ctboard.o(.text)
__main 0x080001f5 Thumb Code 74 datainit_ctboard.o(.text)
Reset_Handler 0x08000271 Thumb Code 8 startup_ctboard.o(.text)
NMI_Handler 0x08000279 Thumb Code 2 startup_ctboard.o(.text)
HardFault_Handler 0x0800027b Thumb Code 2 startup_ctboard.o(.text)
MemManage_Handler 0x0800027d Thumb Code 2 startup_ctboard.o(.text)
BusFault_Handler 0x0800027f Thumb Code 2 startup_ctboard.o(.text)
UsageFault_Handler 0x08000281 Thumb Code 2 startup_ctboard.o(.text)
SVC_Handler 0x08000283 Thumb Code 2 startup_ctboard.o(.text)
DebugMon_Handler 0x08000285 Thumb Code 2 startup_ctboard.o(.text)
PendSV_Handler 0x08000287 Thumb Code 2 startup_ctboard.o(.text)
SysTick_Handler 0x08000289 Thumb Code 2 startup_ctboard.o(.text)
ADC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN1_RX0_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN1_RX1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN1_SCE_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN1_TX_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN2_RX0_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN2_RX1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN2_SCE_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CAN2_TX_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
CRYP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DCMI_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream0_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream6_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream7_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2D_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream0_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream6_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream7_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
ETH_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
ETH_WKUP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI0_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI15_10_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
EXTI9_5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
FLASH_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
FMC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
FPU_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
HASH_RNG_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C1_ER_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C1_EV_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C2_ER_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C2_EV_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C3_ER_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
I2C3_EV_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
LTDC_ER_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
LTDC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_FS_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_FS_WKUP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_EP1_IN_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_EP1_OUT_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_WKUP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
PVD_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
RCC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
RTC_Alarm_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
RTC_WKUP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SAI1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SDIO_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
SPI6_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TAMP_STAMP_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM1_BRK_TIM9_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM1_CC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM1_TRG_COM_TIM11_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM1_UP_TIM10_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM6_DAC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM7_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM8_BRK_TIM12_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM8_CC_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM8_TRG_COM_TIM14_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
TIM8_UP_TIM13_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
UART4_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
UART5_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
UART7_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
UART8_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
USART1_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
USART2_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
USART3_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
USART6_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
WWDG_IRQHandler 0x0800028b Thumb Code 0 startup_ctboard.o(.text)
__system 0x08000295 Thumb Code 8 system_ctboard.o(.text)
system_enter_run 0x0800029d Thumb Code 280 system_ctboard.o(.text)
system_enter_sleep 0x080003f1 Thumb Code 2 system_ctboard.o(.text)
system_enter_stop 0x080003f3 Thumb Code 2 system_ctboard.o(.text)
system_enter_standby 0x080003f5 Thumb Code 2 system_ctboard.o(.text)
hal_fmc_reset 0x080003f9 Thumb Code 60 hal_fmc.o(.text)
hal_fmc_init_sram 0x08000441 Thumb Code 264 hal_fmc.o(.text)
hal_gpio_reset 0x0800054d Thumb Code 68 hal_gpio.o(.text)
hal_gpio_init_input 0x08000599 Thumb Code 156 hal_gpio.o(.text)
hal_gpio_init_analog 0x0800063d Thumb Code 240 hal_gpio.o(.text)
hal_gpio_init_output 0x08000735 Thumb Code 276 hal_gpio.o(.text)
hal_gpio_init_alternate 0x08000851 Thumb Code 262 hal_gpio.o(.text)
hal_gpio_input_read 0x08000957 Thumb Code 6 hal_gpio.o(.text)
hal_gpio_output_read 0x0800095d Thumb Code 6 hal_gpio.o(.text)
hal_gpio_output_write 0x08000965 Thumb Code 20 hal_gpio.o(.text)
hal_gpio_bit_set 0x08000981 Thumb Code 24 hal_gpio.o(.text)
hal_gpio_bit_reset 0x080009a1 Thumb Code 28 hal_gpio.o(.text)
hal_gpio_bit_toggle 0x080009c5 Thumb Code 28 hal_gpio.o(.text)
hal_gpio_irq_set 0x080009e9 Thumb Code 292 hal_gpio.o(.text)
hal_gpio_irq_status 0x08000b25 Thumb Code 24 hal_gpio.o(.text)
hal_gpio_irq_clear 0x08000b41 Thumb Code 12 hal_gpio.o(.text)
hal_pwr_reset 0x08000b51 Thumb Code 16 hal_pwr.o(.text)
hal_pwr_set_backup_domain 0x08000b65 Thumb Code 56 hal_pwr.o(.text)
hal_pwr_set_backup_access 0x08000ba1 Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_wakeup_pin 0x08000bbd Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_flash_powerdown 0x08000bd9 Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_overdrive 0x08000bf5 Thumb Code 4 hal_pwr.o(.text)
hal_pwr_set_underdrive 0x08000bf9 Thumb Code 4 hal_pwr.o(.text)
hal_rcc_reset 0x08000bfd Thumb Code 104 hal_rcc.o(.text)
hal_rcc_set_peripheral 0x08000c85 Thumb Code 228 hal_rcc.o(.text)
hal_rcc_set_osc 0x08000d6d Thumb Code 108 hal_rcc.o(.text)
hal_rcc_setup_pll 0x08000de1 Thumb Code 220 hal_rcc.o(.text)
hal_rcc_setup_clock 0x08000ed5 Thumb Code 80 hal_rcc.o(.text)
Image$$ER_IROM1$$Limit 0x08000f2c Number 0 anon$$obj.o ABSOLUTE
Image$$RW_IRAM1$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE
Image$$RW_IRAM1$$ZI$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE
Stack_Mem 0x20000000 Data 8192 startup_ctboard.o(STACK)
Image$$RW_IRAM1$$ZI$$Limit 0x20002000 Number 0 anon$$obj.o ABSOLUTE
==============================================================================
Memory Map of the image
Image Entry point : 0x08000271
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000f2c, Max: 0x00200000, ABSOLUTE)
Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000f2c, Max: 0x00200000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x08000000 0x08000000 0x000001ac Data RO 26 RESET startup_ctboard.o
0x080001ac 0x080001ac 0x00000024 Code RO 1 .text main.o
0x080001d0 0x080001d0 0x00000024 Code RO 10 .text utils_ctboard.o
0x080001f4 0x080001f4 0x0000007c Code RO 18 .text datainit_ctboard.o
0x08000270 0x08000270 0x00000024 Code RO 27 * .text startup_ctboard.o
0x08000294 0x08000294 0x00000162 Code RO 31 .text system_ctboard.o
0x080003f6 0x080003f6 0x00000002 PAD
0x080003f8 0x080003f8 0x00000154 Code RO 39 .text hal_fmc.o
0x0800054c 0x0800054c 0x00000604 Code RO 47 .text hal_gpio.o
0x08000b50 0x08000b50 0x000000ac Code RO 55 .text hal_pwr.o
0x08000bfc 0x08000bfc 0x00000330 Code RO 63 .text hal_rcc.o
Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000f2c, Size: 0x00002000, Max: 0x00030000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x20000000 - 0x00002000 Zero RW 24 STACK startup_ctboard.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
124 50 0 0 0 456 datainit_ctboard.o
340 16 0 0 0 3832 hal_fmc.o
1540 96 0 0 0 11996 hal_gpio.o
172 20 0 0 0 2127 hal_pwr.o
816 168 0 0 0 5355 hal_rcc.o
36 8 0 0 0 608 main.o
36 8 428 0 8192 824 startup_ctboard.o
354 60 0 0 0 6766 system_ctboard.o
36 0 0 0 0 1748 utils_ctboard.o
----------------------------------------------------------------------
3456 426 428 0 8192 33712 Object Totals
0 0 0 0 0 0 (incl. Generated)
2 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
0 0 0 0 0 0 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
3456 426 428 0 8192 33540 Grand Totals
3456 426 428 0 8192 33540 ELF Image Totals
3456 426 428 0 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 3884 ( 3.79kB)
Total RW Size (RW Data + ZI Data) 8192 ( 8.00kB)
Total ROM Size (Code + RO Data + RW Data) 3884 ( 3.79kB)
==============================================================================

16
bit_manipulations/build/bitmanipulation.sct Normal file
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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}

41
bit_manipulations/build/bitmanipulation_Target 1.dep Normal file
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@ -0,0 +1,41 @@
Dependencies for Project 'bitmanipulation', Target 'Target 1': (DO NOT MODIFY !)
CompilerVersion: 6180000::V6.18::ARMCLANG
F (.\app\main.c)(0x63368DF5)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/main.o -MD)
I (app\utils_ctboard.h)(0x633681EA)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
F (.\app\utils_ctboard.c)(0x633681EA)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/utils_ctboard.o -MD)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (app\utils_ctboard.h)(0x633681EA)
F (RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pd "__UVISION_VERSION SETA 537" --pd "_RTE_ SETA 1" --pd "_RTE_ SETA 1" --list .\build\datainit_ctboard.lst --xref -o .\build\datainit_ctboard.o --depend .\build\datainit_ctboard.d)
F (RTE/Device/CT_Board_HS14_M0/startup_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pd "__UVISION_VERSION SETA 537" --pd "_RTE_ SETA 1" --pd "_RTE_ SETA 1" --list .\build\startup_ctboard.lst --xref -o .\build\startup_ctboard.o --depend .\build\startup_ctboard.d)
F (RTE/Device/CT_Board_HS14_M0/system_ctboard.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/system_ctboard.o -MD)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h)(0x5C6AA868)
F (RTE/HAL/CT_Board_HS14_M0/hal_fmc.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_fmc.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
F (RTE/HAL/CT_Board_HS14_M0/hal_gpio.c)(0x5C5ACEB0)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_gpio.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
F (RTE/HAL/CT_Board_HS14_M0/hal_pwr.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_pwr.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
F (RTE/HAL/CT_Board_HS14_M0/hal_rcc.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_rcc.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)

1
bit_manipulations/build/datainit_ctboard.d Normal file
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@ -0,0 +1 @@
.\build\datainit_ctboard.o: RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s

372
bit_manipulations/build/datainit_ctboard.lst Normal file
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@ -0,0 +1,372 @@
ARM Macro Assembler Page 1
1 00000000 ;* -----------------------------------------------------
-------------
2 00000000 ;* -- _____ ______ _____
-
3 00000000 ;* -- |_ _| | ____|/ ____|
-
4 00000000 ;* -- | | _ __ | |__ | (___ Institute of Embedded
Systems -
5 00000000 ;* -- | | | '_ \| __| \___ \ Zurich University of
-
6 00000000 ;* -- _| |_| | | | |____ ____) | Applied Sciences
-
7 00000000 ;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Swit
zerland -
8 00000000 ;* -----------------------------------------------------
-------------
9 00000000 ;* --
10 00000000 ;* -- Project : CT Board - Cortex M4
11 00000000 ;* -- Description : Data Segment initialisation.
12 00000000 ;* --
13 00000000 ;* -- $Id$
14 00000000 ;* -----------------------------------------------------
-------------
15 00000000
16 00000000
17 00000000 ; ------------------------------------------------------
-------------
18 00000000 ; -- __Main
19 00000000 ; ------------------------------------------------------
-------------
20 00000000
21 00000000 AREA |.text|, CODE, READONLY
22 00000000
23 00000000 IMPORT main
24 00000000
25 00000000 EXPORT __main
26 00000000
27 00000000 __main PROC
28 00000000
29 00000000 ; initialize RW and ZI data - this includes heap and sta
ck for the -ro=... -rw=... -entry=... linking cmd args..
.
30 00000000 IMPORT |Image$$RO$$Limit| [WEAK]
31 00000000 IMPORT |Image$$RW$$Base| [WEAK]
32 00000000 IMPORT |Image$$ZI$$Base| [WEAK]
33 00000000 IMPORT |Image$$ZI$$Limit| [WEAK]
34 00000000 ; ...or from auto generated scatter file. Needs linker o
ption: --diag_suppress 6314
35 00000000 IMPORT |Image$$ER_IROM1$$Limit| [W
EAK]
36 00000000 IMPORT |Image$$RW_IRAM1$$Base| [W
EAK]
37 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Base| [W
EAK]
38 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [W
EAK]
39 00000000 ; import stack parameter
40 00000000 IMPORT Stack_Size [WEAK]
41 00000000 IMPORT Stack_Mem [WEAK]
ARM Macro Assembler Page 2
42 00000000
43 00000000 ; switch between command line generated regions and auto
scatter file generated regions
44 00000000 4912 LDR R1, =|Image$$RO$$Limit|
45 00000002 2900 CMP R1,#0
46 00000004 D004 BEQ ScatterFileSymbols
47 00000006 CommandLineSymbols
48 00000006 4A12 LDR R2, =|Image$$RW$$Base| ; start
of the RW data in R
AM
49 00000008 4B12 LDR R3, =|Image$$ZI$$Base| ; end of
the RW data in RAM
50 0000000A 461D MOV R5, R3 ; start of zero ini
tialized data
51 0000000C 4E12 LDR R6, =|Image$$ZI$$Limit| ; end o
f zero initialized
data
52 0000000E E009 B CondRWLoop
53 00000010 ScatterFileSymbols
54 00000010 4912 LDR R1, =|Image$$ER_IROM1$$Limit| ;
start of flashed i
nitial RW data
55 00000012 4A13 LDR R2, =|Image$$RW_IRAM1$$Base| ;
start of the RW dat
a in RAM
56 00000014 4B13 LDR R3, =|Image$$RW_IRAM1$$ZI$$Base
|
; end of the RW dat
a in RAM
57 00000016 461D MOV R5, R3 ; start of zero ini
tialized data
58 00000018 4E13 LDR R6, =|Image$$RW_IRAM1$$ZI$$Limi
t|
; end of zero initi
alized data
59 0000001A E003 B CondRWLoop
60 0000001C
61 0000001C ; init non-zero data
62 0000001C 680C LoopRWCopy
LDR R4, [R1]
63 0000001E 6014 STR R4, [R2]
64 00000020 1D09 ADDS R1, R1, #4
65 00000022 1D12 ADDS R2, R2, #4
66 00000024 429A CondRWLoop
CMP R2, R3
67 00000026 D1F9 BNE LoopRWCopy
68 00000028
69 00000028 ; init zero-initialized data
70 00000028 462A MOV R2, R5
71 0000002A 4633 MOV R3, R6
72 0000002C 2400 MOVS R4, #0
73 0000002E E001 B CondZILoop
74 00000030 6014 LoopZICopy
STR R4, [R2]
75 00000032 1D12 ADDS R2, R2, #4
76 00000034 429A CondZILoop
CMP R2, R3
77 00000036 D1FB BNE LoopZICopy
ARM Macro Assembler Page 3
78 00000038
79 00000038 ; fingerprint stack section
80 00000038 480C LDR R0, =Stack_Mem
81 0000003A 490D LDR R1, =Stack_Size
82 0000003C 4A0D LDR R2, =0xEFBEADDE ; stack fingerp
rint (little endian
!)
83 0000003E 6002 LoopStack
STR R2, [R0]
84 00000040 1D00 ADDS R0, R0, #4
85 00000042 3904 SUBS R1, #4
86 00000044 D1FB BNE LoopStack
87 00000046
88 00000046 ; go to the user main function
89 00000046 480C LDR R0, =main
90 00000048 4700 BX R0
91 0000004A ENDP
92 0000004A
93 0000004A
94 0000004A ; ------------------------------------------------------
-------------
95 0000004A ; -- End of file
96 0000004A ; ------------------------------------------------------
-------------
97 0000004A
98 0000004A 00 00 ALIGN
99 0000004C
100 0000004C END
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
EFBEADDE
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
ild\datainit_ctboard.d -o.\build\datainit_ctboard.o -I.\RTE\_Target_1 -IC:\User
s\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Us
ers\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -I
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --p
redefine="__EVAL SETA 1" --predefine="__UVISION_VERSION SETA 537" --predefine="
_RTE_ SETA 1" --predefine="_RTE_ SETA 1" --list=.\build\datainit_ctboard.lst RT
E/Device/CT_Board_HS14_M0/datainit_ctboard.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 21 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
None
Comment: .text unused
CommandLineSymbols 00000006
Symbol: CommandLineSymbols
Definitions
At line 47 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
None
Comment: CommandLineSymbols unused
CondRWLoop 00000024
Symbol: CondRWLoop
Definitions
At line 66 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 52 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
At line 59 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
CondZILoop 00000034
Symbol: CondZILoop
Definitions
At line 76 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 73 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: CondZILoop used once
LoopRWCopy 0000001C
Symbol: LoopRWCopy
Definitions
At line 62 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 67 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopRWCopy used once
LoopStack 0000003E
Symbol: LoopStack
Definitions
At line 83 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 86 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopStack used once
LoopZICopy 00000030
Symbol: LoopZICopy
Definitions
At line 74 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 77 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopZICopy used once
ScatterFileSymbols 00000010
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Symbol: ScatterFileSymbols
Definitions
At line 53 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 46 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: ScatterFileSymbols used once
__main 00000000
Symbol: __main
Definitions
At line 27 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 25 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: __main used once
9 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
Image$$ER_IROM1$$Limit 00000000
Symbol: Image$$ER_IROM1$$Limit
Definitions
At line 35 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 54 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ER_IROM1$$Limit used once
Image$$RO$$Limit 00000000
Symbol: Image$$RO$$Limit
Definitions
At line 30 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 44 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RO$$Limit used once
Image$$RW$$Base 00000000
Symbol: Image$$RW$$Base
Definitions
At line 31 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 48 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW$$Base used once
Image$$RW_IRAM1$$Base 00000000
Symbol: Image$$RW_IRAM1$$Base
Definitions
At line 36 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 55 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$Base used once
Image$$RW_IRAM1$$ZI$$Base 00000000
Symbol: Image$$RW_IRAM1$$ZI$$Base
Definitions
At line 37 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 56 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$ZI$$Base used once
Image$$RW_IRAM1$$ZI$$Limit 00000000
Symbol: Image$$RW_IRAM1$$ZI$$Limit
Definitions
At line 38 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 58 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$ZI$$Limit used once
Image$$ZI$$Base 00000000
Symbol: Image$$ZI$$Base
Definitions
At line 32 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 49 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ZI$$Base used once
Image$$ZI$$Limit 00000000
Symbol: Image$$ZI$$Limit
ARM Macro Assembler Page 2 Alphabetic symbol ordering
External symbols
Definitions
At line 33 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 51 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ZI$$Limit used once
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 41 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 80 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Stack_Mem used once
Stack_Size 00000000
Symbol: Stack_Size
Definitions
At line 40 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 81 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Stack_Size used once
main 00000000
Symbol: main
Definitions
At line 23 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 89 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: main used once
11 symbols
355 symbols in table

BIN
bit_manipulations/build/datainit_ctboard.o Normal file
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Binary file not shown.

5
bit_manipulations/build/hal_fmc.d Normal file
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./build/hal_fmc.o: RTE\HAL\CT_Board_HS14_M0\hal_fmc.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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bit_manipulations/build/hal_gpio.d Normal file
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./build/hal_gpio.o: RTE\HAL\CT_Board_HS14_M0\hal_gpio.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h

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./build/hal_pwr.o: RTE\HAL\CT_Board_HS14_M0\hal_pwr.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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./build/hal_rcc.o: RTE\HAL\CT_Board_HS14_M0\hal_rcc.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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./build/main.o: app\main.c app\utils_ctboard.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h

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.\build\startup_ctboard.o: RTE/Device/CT_Board_HS14_M0/startup_ctboard.s

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./build/system_ctboard.o: RTE\Device\CT_Board_HS14_M0\system_ctboard.c \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h

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./build/utils_ctboard.o: app\utils_ctboard.c \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h app\utils_ctboard.h

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