solved Task 3a
This commit is contained in:
Schrom01
@@ -0,0 +1,100 @@
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;* ------------------------------------------------------------------
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;* -- _____ ______ _____ -
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;* -- |_ _| | ____|/ ____| -
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;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
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;* -- | | | '_ \| __| \___ \ Zurich University of -
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;* -- _| |_| | | | |____ ____) | Applied Sciences -
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;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
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;* ------------------------------------------------------------------
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;* --
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;* -- Project : CT Board - Cortex M4
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;* -- Description : Data Segment initialisation.
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;* --
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;* -- $Id$
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;* ------------------------------------------------------------------
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; -------------------------------------------------------------------
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; -- __Main
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; -------------------------------------------------------------------
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AREA |.text|, CODE, READONLY
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IMPORT main
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EXPORT __main
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__main PROC
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; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
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IMPORT |Image$$RO$$Limit| [WEAK]
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IMPORT |Image$$RW$$Base| [WEAK]
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IMPORT |Image$$ZI$$Base| [WEAK]
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IMPORT |Image$$ZI$$Limit| [WEAK]
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; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
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IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
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IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
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IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
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IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
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; import stack parameter
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IMPORT Stack_Size [WEAK]
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IMPORT Stack_Mem [WEAK]
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; switch between command line generated regions and auto scatter file generated regions
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LDR R1, =|Image$$RO$$Limit|
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CMP R1,#0
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BEQ ScatterFileSymbols
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CommandLineSymbols
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LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
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LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
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MOV R5, R3 ; start of zero initialized data
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LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
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B CondRWLoop
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ScatterFileSymbols
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LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
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LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
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LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
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MOV R5, R3 ; start of zero initialized data
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LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
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B CondRWLoop
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; init non-zero data
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LoopRWCopy LDR R4, [R1]
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STR R4, [R2]
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ADDS R1, R1, #4
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ADDS R2, R2, #4
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CondRWLoop CMP R2, R3
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BNE LoopRWCopy
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; init zero-initialized data
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MOV R2, R5
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MOV R3, R6
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MOVS R4, #0
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B CondZILoop
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LoopZICopy STR R4, [R2]
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ADDS R2, R2, #4
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CondZILoop CMP R2, R3
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BNE LoopZICopy
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; fingerprint stack section
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LDR R0, =Stack_Mem
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LDR R1, =Stack_Size
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LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
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LoopStack STR R2, [R0]
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ADDS R0, R0, #4
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SUBS R1, #4
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BNE LoopStack
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; go to the user main function
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LDR R0, =main
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BX R0
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ENDP
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; -------------------------------------------------------------------
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; -- End of file
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; -------------------------------------------------------------------
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ALIGN
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END
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@@ -0,0 +1,439 @@
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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
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;* File Name : startup_stm32f429_439xx.s
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;* Author : MCD Application Team
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;* Version : V1.3.0
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;* Date : 08-November-2013
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;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Configure the system clock and the external SRAM/SDRAM mounted
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;* on STM324x9I-EVAL boards to be used as data memory
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;* (optional, to be enabled by user)
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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; You may not use this file except in compliance with the License.
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; You may obtain a copy of the License at:
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;
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; http://www.st.com/software_license_agreement_liberty_v2
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00002000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT Stack_Size
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EXPORT Stack_Mem
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000800
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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DCD CAN1_TX_IRQHandler ; CAN1 TX
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DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
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DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
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DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD FMC_IRQHandler ; FMC
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DCD SDIO_IRQHandler ; SDIO
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD ETH_IRQHandler ; Ethernet
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DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
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DCD CAN2_TX_IRQHandler ; CAN2 TX
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DCD CAN2_RX0_IRQHandler ; CAN2 RX0
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DCD CAN2_RX1_IRQHandler ; CAN2 RX1
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DCD CAN2_SCE_IRQHandler ; CAN2 SCE
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
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DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
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DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
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DCD OTG_HS_IRQHandler ; USB OTG HS
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DCD DCMI_IRQHandler ; DCMI
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DCD CRYP_IRQHandler ; CRYP crypto
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DCD HASH_RNG_IRQHandler ; Hash and Rng
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DCD FPU_IRQHandler ; FPU
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DCD UART7_IRQHandler ; UART7
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DCD UART8_IRQHandler ; UART8
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DCD SPI4_IRQHandler ; SPI4
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DCD SPI5_IRQHandler ; SPI5
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DCD SPI6_IRQHandler ; SPI6
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DCD SAI1_IRQHandler ; SAI1
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DCD LTDC_IRQHandler ; LTDC
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DCD LTDC_ER_IRQHandler ; LTDC error
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DCD DMA2D_IRQHandler ; DMA2D
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __system
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IMPORT __main
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ENTRY
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LDR R0, =__system
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Stream0_IRQHandler [WEAK]
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EXPORT DMA1_Stream1_IRQHandler [WEAK]
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EXPORT DMA1_Stream2_IRQHandler [WEAK]
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EXPORT DMA1_Stream3_IRQHandler [WEAK]
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EXPORT DMA1_Stream4_IRQHandler [WEAK]
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EXPORT DMA1_Stream5_IRQHandler [WEAK]
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EXPORT DMA1_Stream6_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT CAN1_TX_IRQHandler [WEAK]
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EXPORT CAN1_RX0_IRQHandler [WEAK]
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EXPORT CAN1_RX1_IRQHandler [WEAK]
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EXPORT CAN1_SCE_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
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||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
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EXPORT TIM8_CC_IRQHandler [WEAK]
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||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
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||||
EXPORT FMC_IRQHandler [WEAK]
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||||
EXPORT SDIO_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
|
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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||||
EXPORT UART5_IRQHandler [WEAK]
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||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
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||||
EXPORT TIM7_IRQHandler [WEAK]
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||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
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||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
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||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
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EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
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EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
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EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
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EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
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EXPORT DCMI_IRQHandler [WEAK]
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||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@@ -0,0 +1,290 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Interface of module system_ctboard.
|
||||
* Description : Basic system configuration.
|
||||
* * initialize system clock
|
||||
* * initialize FMC (SRAM & GPIO)
|
||||
*
|
||||
* GPIO FMC pin assignment:
|
||||
*
|
||||
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
|
||||
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
|
||||
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
|
||||
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
|
||||
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
|
||||
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
|
||||
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
|
||||
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
|
||||
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
|
||||
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
|
||||
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
|
||||
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
|
||||
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
|
||||
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
|
||||
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
|
||||
* | PE15 > FMC_D12 | |
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Standard includes */
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* User includes */
|
||||
#include "system_ctboard.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
#include "reg_ctboard.h"
|
||||
|
||||
|
||||
/* -- Macros (LCD)
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define LCD_WAIT 0x1fff
|
||||
|
||||
|
||||
/* -- Macros (FMC)
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define FMC_PORTD_PINMASK 0xfffb
|
||||
#define FMC_PORTE_PINMASK 0xffff
|
||||
#define FMC_PORTF_PINMASK 0xf03f
|
||||
#define FMC_PORTG_PINMASK 0x363f
|
||||
|
||||
|
||||
/* -- Local function declarations
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
static void init_SystemClock(void);
|
||||
static void init_FPU(void);
|
||||
static void init_FMC_SRAM(void);
|
||||
static void init_LCD(void);
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Entry point used in startup.
|
||||
*/
|
||||
void __system(void)
|
||||
{
|
||||
system_enter_run();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header files
|
||||
*/
|
||||
void system_enter_run(void)
|
||||
{
|
||||
/* Initialize RCC / system clock */
|
||||
init_SystemClock();
|
||||
|
||||
/* Iitialize FPU */
|
||||
init_FPU();
|
||||
|
||||
/* Initialize SRAM interface */
|
||||
init_FMC_SRAM();
|
||||
|
||||
/* Initialize LCD on CT-Board */
|
||||
init_LCD();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_sleep(hal_pwr_lp_entry_t entry)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_standby(void)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/* -- Local function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Configures the System clock source, PLL Multiplier and Divider
|
||||
* factors, AHB/APBx prescalers and Flash settings.
|
||||
*/
|
||||
static void init_SystemClock(void)
|
||||
{
|
||||
hal_rcc_pll_init_t pll_init;
|
||||
hal_rcc_clk_init_t clk_init;
|
||||
|
||||
/* Enable used periphery */
|
||||
PWR_ENABLE();
|
||||
|
||||
/* Reset */
|
||||
hal_rcc_reset();
|
||||
PWR_RESET();
|
||||
|
||||
/* Enable HSE oscillator and proceed if ok */
|
||||
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
|
||||
/* Select regulator voltage output Scale 1 mode */
|
||||
RCC->APB1ENR |= 0x00000000;
|
||||
PWR->CR |= 0x0000c000;
|
||||
|
||||
/* Configure PLL */
|
||||
pll_init.source = HAL_RCC_OSC_HSE;
|
||||
pll_init.m_divider = 4u;
|
||||
pll_init.n_factor = 168u;
|
||||
pll_init.p_divider = 2u;
|
||||
pll_init.q_divider = 7u;
|
||||
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
|
||||
|
||||
/* Enable PLL */
|
||||
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
|
||||
|
||||
/* Enable overdrive to allow system clock >= 168 MHz */
|
||||
hal_pwr_set_overdrive(ENABLE);
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache
|
||||
* and wait state */
|
||||
FLASH->ACR = 0x00000705;
|
||||
|
||||
/* Setup system clock */
|
||||
clk_init.osc = HAL_RCC_OSC_PLL;
|
||||
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
|
||||
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
|
||||
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
|
||||
hal_rcc_setup_clock(clk_init);
|
||||
|
||||
} else {
|
||||
/* If HSE fails to start-up, the application will have wrong clock con-
|
||||
figuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Initialize the floating point unit in M4 mode.
|
||||
*/
|
||||
static void init_FPU(void)
|
||||
{
|
||||
#ifdef PLATFORM_M4
|
||||
/* No documentation about this, even the registers... */
|
||||
|
||||
/* set CP10 and CP11 Full Access */
|
||||
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Setup the flexible memory controller. This function configures the SRAM
|
||||
* interface for accessing the periphery on the CT Board.
|
||||
*/
|
||||
static void init_FMC_SRAM(void)
|
||||
{
|
||||
#ifndef NO_FMC
|
||||
|
||||
hal_gpio_output_t gpio_init;
|
||||
hal_fmc_sram_init_t sram_init;
|
||||
hal_fmc_sram_timing_t sram_timing;
|
||||
|
||||
/* Enable used peripherals */
|
||||
GPIOD_ENABLE();
|
||||
GPIOE_ENABLE();
|
||||
GPIOF_ENABLE();
|
||||
GPIOG_ENABLE();
|
||||
FMC_ENABLE();
|
||||
|
||||
/* Configure the involved GPIO pins to AF12 (FMC) */
|
||||
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
|
||||
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
|
||||
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
|
||||
|
||||
/* GPIOD configuration (pins: 0,1,3-15) */
|
||||
gpio_init.pins = FMC_PORTD_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOE configuration (pins: 0-15) */
|
||||
gpio_init.pins = FMC_PORTE_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOF configuration (pins: 0-5,12-15) */
|
||||
gpio_init.pins = FMC_PORTF_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
|
||||
gpio_init.pins = FMC_PORTG_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
|
||||
/* Initialize the synchronous PSRAM on bank 1 */
|
||||
sram_init.address_mux = DISABLE;
|
||||
sram_init.type = HAL_FMC_TYPE_PSRAM;
|
||||
sram_init.width = HAL_FMC_WIDTH_16B;
|
||||
sram_init.read_burst = ENABLE;
|
||||
sram_init.write_enable = ENABLE;
|
||||
sram_init.write_burst = ENABLE;
|
||||
sram_init.continous_clock = ENABLE;
|
||||
|
||||
sram_timing.bus_turnaround = 1u;
|
||||
sram_timing.clk_divider = 15u;
|
||||
sram_timing.data_latency = 2u;
|
||||
|
||||
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
|
||||
|
||||
|
||||
/* Initialize the asynchronous SRAM on bank 2 */
|
||||
sram_init.address_mux = DISABLE;
|
||||
sram_init.type = HAL_FMC_TYPE_SRAM;
|
||||
sram_init.width = HAL_FMC_WIDTH_16B;
|
||||
sram_init.read_burst = DISABLE;
|
||||
sram_init.write_enable = DISABLE;
|
||||
sram_init.write_burst = DISABLE;
|
||||
sram_init.continous_clock = DISABLE;
|
||||
|
||||
sram_timing.bus_turnaround = 1u;
|
||||
sram_timing.address_setup = 11u;
|
||||
sram_timing.address_hold = 5u;
|
||||
sram_timing.data_setup = 11u;
|
||||
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
|
||||
|
||||
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Wait for the LCD controller on the CT Board to be initialized.
|
||||
* \TODO Possibly adjust LCD controller on CPLD to set status bit
|
||||
* and wait for it in this function.
|
||||
*/
|
||||
static void init_LCD(void)
|
||||
{
|
||||
#ifndef NO_FMC
|
||||
uint32_t wait_for_lcd = LCD_WAIT;
|
||||
for(; wait_for_lcd > 0; wait_for_lcd--);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,100 @@
|
||||
;* ------------------------------------------------------------------
|
||||
;* -- _____ ______ _____ -
|
||||
;* -- |_ _| | ____|/ ____| -
|
||||
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
;* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
;* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
;* ------------------------------------------------------------------
|
||||
;* --
|
||||
;* -- Project : CT Board - Cortex M4
|
||||
;* -- Description : Data Segment initialisation.
|
||||
;* --
|
||||
;* -- $Id$
|
||||
;* ------------------------------------------------------------------
|
||||
|
||||
|
||||
; -------------------------------------------------------------------
|
||||
; -- __Main
|
||||
; -------------------------------------------------------------------
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
IMPORT main
|
||||
|
||||
EXPORT __main
|
||||
|
||||
__main PROC
|
||||
|
||||
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
|
||||
IMPORT |Image$$RO$$Limit| [WEAK]
|
||||
IMPORT |Image$$RW$$Base| [WEAK]
|
||||
IMPORT |Image$$ZI$$Base| [WEAK]
|
||||
IMPORT |Image$$ZI$$Limit| [WEAK]
|
||||
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
|
||||
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
|
||||
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
|
||||
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
|
||||
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
|
||||
; import stack parameter
|
||||
IMPORT Stack_Size [WEAK]
|
||||
IMPORT Stack_Mem [WEAK]
|
||||
|
||||
; switch between command line generated regions and auto scatter file generated regions
|
||||
LDR R1, =|Image$$RO$$Limit|
|
||||
CMP R1,#0
|
||||
BEQ ScatterFileSymbols
|
||||
CommandLineSymbols
|
||||
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
|
||||
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
|
||||
MOV R5, R3 ; start of zero initialized data
|
||||
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
|
||||
B CondRWLoop
|
||||
ScatterFileSymbols
|
||||
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
|
||||
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
|
||||
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
|
||||
MOV R5, R3 ; start of zero initialized data
|
||||
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
|
||||
B CondRWLoop
|
||||
|
||||
; init non-zero data
|
||||
LoopRWCopy LDR R4, [R1]
|
||||
STR R4, [R2]
|
||||
ADDS R1, R1, #4
|
||||
ADDS R2, R2, #4
|
||||
CondRWLoop CMP R2, R3
|
||||
BNE LoopRWCopy
|
||||
|
||||
; init zero-initialized data
|
||||
MOV R2, R5
|
||||
MOV R3, R6
|
||||
MOVS R4, #0
|
||||
B CondZILoop
|
||||
LoopZICopy STR R4, [R2]
|
||||
ADDS R2, R2, #4
|
||||
CondZILoop CMP R2, R3
|
||||
BNE LoopZICopy
|
||||
|
||||
; fingerprint stack section
|
||||
LDR R0, =Stack_Mem
|
||||
LDR R1, =Stack_Size
|
||||
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
|
||||
LoopStack STR R2, [R0]
|
||||
ADDS R0, R0, #4
|
||||
SUBS R1, #4
|
||||
BNE LoopStack
|
||||
|
||||
; go to the user main function
|
||||
LDR R0, =main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; -------------------------------------------------------------------
|
||||
; -- End of file
|
||||
; -------------------------------------------------------------------
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,439 @@
|
||||
;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f429_439xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.3.0
|
||||
;* Date : 08-November-2013
|
||||
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the system clock and the external SRAM/SDRAM mounted
|
||||
;* on STM324x9I-EVAL boards to be used as data memory
|
||||
;* (optional, to be enabled by user)
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00002000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT Stack_Size
|
||||
EXPORT Stack_Mem
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000800
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYP crypto
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __system
|
||||
IMPORT __main
|
||||
ENTRY
|
||||
|
||||
LDR R0, =__system
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@@ -0,0 +1,290 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Interface of module system_ctboard.
|
||||
* Description : Basic system configuration.
|
||||
* * initialize system clock
|
||||
* * initialize FMC (SRAM & GPIO)
|
||||
*
|
||||
* GPIO FMC pin assignment:
|
||||
*
|
||||
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
|
||||
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
|
||||
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
|
||||
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
|
||||
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
|
||||
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
|
||||
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
|
||||
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
|
||||
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
|
||||
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
|
||||
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
|
||||
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
|
||||
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
|
||||
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
|
||||
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
|
||||
* | PE15 > FMC_D12 | |
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Standard includes */
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* User includes */
|
||||
#include "system_ctboard.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
#include "reg_ctboard.h"
|
||||
|
||||
|
||||
/* -- Macros (LCD)
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define LCD_WAIT 0x1fff
|
||||
|
||||
|
||||
/* -- Macros (FMC)
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define FMC_PORTD_PINMASK 0xfffb
|
||||
#define FMC_PORTE_PINMASK 0xffff
|
||||
#define FMC_PORTF_PINMASK 0xf03f
|
||||
#define FMC_PORTG_PINMASK 0x363f
|
||||
|
||||
|
||||
/* -- Local function declarations
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
static void init_SystemClock(void);
|
||||
static void init_FPU(void);
|
||||
static void init_FMC_SRAM(void);
|
||||
static void init_LCD(void);
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Entry point used in startup.
|
||||
*/
|
||||
void __system(void)
|
||||
{
|
||||
system_enter_run();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header files
|
||||
*/
|
||||
void system_enter_run(void)
|
||||
{
|
||||
/* Initialize RCC / system clock */
|
||||
init_SystemClock();
|
||||
|
||||
/* Iitialize FPU */
|
||||
init_FPU();
|
||||
|
||||
/* Initialize SRAM interface */
|
||||
init_FMC_SRAM();
|
||||
|
||||
/* Initialize LCD on CT-Board */
|
||||
init_LCD();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_sleep(hal_pwr_lp_entry_t entry)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void system_enter_standby(void)
|
||||
{
|
||||
/** \note Implement this function if needed. */
|
||||
}
|
||||
|
||||
|
||||
/* -- Local function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Configures the System clock source, PLL Multiplier and Divider
|
||||
* factors, AHB/APBx prescalers and Flash settings.
|
||||
*/
|
||||
static void init_SystemClock(void)
|
||||
{
|
||||
hal_rcc_pll_init_t pll_init;
|
||||
hal_rcc_clk_init_t clk_init;
|
||||
|
||||
/* Enable used periphery */
|
||||
PWR_ENABLE();
|
||||
|
||||
/* Reset */
|
||||
hal_rcc_reset();
|
||||
PWR_RESET();
|
||||
|
||||
/* Enable HSE oscillator and proceed if ok */
|
||||
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
|
||||
/* Select regulator voltage output Scale 1 mode */
|
||||
RCC->APB1ENR |= 0x00000000;
|
||||
PWR->CR |= 0x0000c000;
|
||||
|
||||
/* Configure PLL */
|
||||
pll_init.source = HAL_RCC_OSC_HSE;
|
||||
pll_init.m_divider = 4u;
|
||||
pll_init.n_factor = 168u;
|
||||
pll_init.p_divider = 2u;
|
||||
pll_init.q_divider = 7u;
|
||||
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
|
||||
|
||||
/* Enable PLL */
|
||||
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
|
||||
|
||||
/* Enable overdrive to allow system clock >= 168 MHz */
|
||||
hal_pwr_set_overdrive(ENABLE);
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache
|
||||
* and wait state */
|
||||
FLASH->ACR = 0x00000705;
|
||||
|
||||
/* Setup system clock */
|
||||
clk_init.osc = HAL_RCC_OSC_PLL;
|
||||
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
|
||||
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
|
||||
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
|
||||
hal_rcc_setup_clock(clk_init);
|
||||
|
||||
} else {
|
||||
/* If HSE fails to start-up, the application will have wrong clock con-
|
||||
figuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Initialize the floating point unit in M4 mode.
|
||||
*/
|
||||
static void init_FPU(void)
|
||||
{
|
||||
#ifdef PLATFORM_M4
|
||||
/* No documentation about this, even the registers... */
|
||||
|
||||
/* set CP10 and CP11 Full Access */
|
||||
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Setup the flexible memory controller. This function configures the SRAM
|
||||
* interface for accessing the periphery on the CT Board.
|
||||
*/
|
||||
static void init_FMC_SRAM(void)
|
||||
{
|
||||
#ifndef NO_FMC
|
||||
|
||||
hal_gpio_output_t gpio_init;
|
||||
hal_fmc_sram_init_t sram_init;
|
||||
hal_fmc_sram_timing_t sram_timing;
|
||||
|
||||
/* Enable used peripherals */
|
||||
GPIOD_ENABLE();
|
||||
GPIOE_ENABLE();
|
||||
GPIOF_ENABLE();
|
||||
GPIOG_ENABLE();
|
||||
FMC_ENABLE();
|
||||
|
||||
/* Configure the involved GPIO pins to AF12 (FMC) */
|
||||
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
|
||||
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
|
||||
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
|
||||
|
||||
/* GPIOD configuration (pins: 0,1,3-15) */
|
||||
gpio_init.pins = FMC_PORTD_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOE configuration (pins: 0-15) */
|
||||
gpio_init.pins = FMC_PORTE_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOF configuration (pins: 0-5,12-15) */
|
||||
gpio_init.pins = FMC_PORTF_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
|
||||
gpio_init.pins = FMC_PORTG_PINMASK;
|
||||
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
|
||||
|
||||
|
||||
/* Initialize the synchronous PSRAM on bank 1 */
|
||||
sram_init.address_mux = DISABLE;
|
||||
sram_init.type = HAL_FMC_TYPE_PSRAM;
|
||||
sram_init.width = HAL_FMC_WIDTH_16B;
|
||||
sram_init.read_burst = ENABLE;
|
||||
sram_init.write_enable = ENABLE;
|
||||
sram_init.write_burst = ENABLE;
|
||||
sram_init.continous_clock = ENABLE;
|
||||
|
||||
sram_timing.bus_turnaround = 1u;
|
||||
sram_timing.clk_divider = 15u;
|
||||
sram_timing.data_latency = 2u;
|
||||
|
||||
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
|
||||
|
||||
|
||||
/* Initialize the asynchronous SRAM on bank 2 */
|
||||
sram_init.address_mux = DISABLE;
|
||||
sram_init.type = HAL_FMC_TYPE_SRAM;
|
||||
sram_init.width = HAL_FMC_WIDTH_16B;
|
||||
sram_init.read_burst = DISABLE;
|
||||
sram_init.write_enable = DISABLE;
|
||||
sram_init.write_burst = DISABLE;
|
||||
sram_init.continous_clock = DISABLE;
|
||||
|
||||
sram_timing.bus_turnaround = 1u;
|
||||
sram_timing.address_setup = 11u;
|
||||
sram_timing.address_hold = 5u;
|
||||
sram_timing.data_setup = 11u;
|
||||
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
|
||||
|
||||
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Wait for the LCD controller on the CT Board to be initialized.
|
||||
* \TODO Possibly adjust LCD controller on CPLD to set status bit
|
||||
* and wait for it in this function.
|
||||
*/
|
||||
static void init_LCD(void)
|
||||
{
|
||||
#ifndef NO_FMC
|
||||
uint32_t wait_for_lcd = LCD_WAIT;
|
||||
for(; wait_for_lcd > 0; wait_for_lcd--);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,143 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_fmc.
|
||||
*
|
||||
* The hardware abstraction layer for the memory controller.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_fmc.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define MASK_PERIPH_FMC (0x00000001)
|
||||
#define MASK_SRAM_ENABLE (0x00000001)
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_fmc_reset(hal_fmc_bank_t bank)
|
||||
{
|
||||
switch (bank) {
|
||||
default:
|
||||
case HAL_FMC_SRAM_BANK1:
|
||||
FMC->SRAM.BCR1 = 0x000030db;
|
||||
FMC->SRAM.BTR1 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK2:
|
||||
FMC->SRAM.BCR2 = 0x000030d2;
|
||||
FMC->SRAM.BTR2 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK3:
|
||||
FMC->SRAM.BCR3 = 0x000030d2;
|
||||
FMC->SRAM.BTR3 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK4:
|
||||
FMC->SRAM.BCR4 = 0x000030d2;
|
||||
FMC->SRAM.BTR4 = 0x0fffffff;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_fmc_init_sram(hal_fmc_bank_t bank,
|
||||
hal_fmc_sram_init_t init,
|
||||
hal_fmc_sram_timing_t timing)
|
||||
{
|
||||
uint32_t reg_cr = 0, reg_tr = 0;
|
||||
|
||||
/* Input check */
|
||||
timing.address_setup &= 0xf;
|
||||
timing.address_hold &= 0xf;
|
||||
if (timing.address_hold < 1u) timing.address_hold = 1u;
|
||||
timing.data_setup &= 0xff;
|
||||
if (timing.data_setup < 1u) timing.data_setup = 1u;
|
||||
timing.bus_turnaround &= 0xf;
|
||||
|
||||
/* Input check clock divider (2..16) */
|
||||
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
|
||||
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
|
||||
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
|
||||
|
||||
/* Input check data latency (2..17) */
|
||||
if (timing.data_latency > 17u) timing.data_latency = 17u;
|
||||
if (timing.data_latency < 2u) timing.data_latency = 2u;
|
||||
timing.data_latency -= 2u; // 0b0000 -> latency = 2
|
||||
|
||||
/* Process boolean parameter */
|
||||
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
|
||||
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
|
||||
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
|
||||
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
|
||||
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
|
||||
|
||||
/* Process non boolean parameter */
|
||||
reg_cr |= (init.type << 2u);
|
||||
reg_cr |= (init.width << 4u);
|
||||
|
||||
/* Process timing for async. SRAM */
|
||||
if (init.type == HAL_FMC_TYPE_SRAM) {
|
||||
reg_tr |= (timing.address_setup << 0u);
|
||||
reg_tr |= (timing.address_hold << 4u);
|
||||
reg_tr |= (timing.data_setup << 8u);
|
||||
reg_tr |= (timing.mode << 28u);
|
||||
}
|
||||
/* Process timing for sync. PSRAM */
|
||||
else if (init.type == HAL_FMC_TYPE_PSRAM) {
|
||||
reg_tr |= (timing.clk_divider << 20u);
|
||||
reg_tr |= (timing.data_latency << 24u);
|
||||
}
|
||||
/* Process bus turnaround time */
|
||||
reg_tr |= (timing.bus_turnaround << 16u);
|
||||
|
||||
/* Write register */
|
||||
switch (bank) {
|
||||
default:
|
||||
case HAL_FMC_SRAM_BANK1:
|
||||
FMC->SRAM.BCR1 = reg_cr;
|
||||
FMC->SRAM.BTR1 = reg_tr;
|
||||
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK2:
|
||||
FMC->SRAM.BCR2 = reg_cr;
|
||||
FMC->SRAM.BTR2 = reg_tr;
|
||||
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK3:
|
||||
FMC->SRAM.BCR3 = reg_cr;
|
||||
FMC->SRAM.BTR3 = reg_tr;
|
||||
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK4:
|
||||
FMC->SRAM.BCR4 = reg_cr;
|
||||
FMC->SRAM.BTR4 = reg_tr;
|
||||
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,412 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_gpio.
|
||||
*
|
||||
* The hardware abstraction layer for the GPIO periphery.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_gpio.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define NVIC_OFFSET_1_4 ( 6u)
|
||||
#define NVIC_OFFSET_5_9 (23u)
|
||||
#define NVIC_OFFSET_10_15 ( 8u)
|
||||
|
||||
|
||||
/* -- Local function declarations
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
static uint32_t create_pattern_mask(uint16_t pins,
|
||||
uint8_t pattern,
|
||||
uint8_t pattern_bit_width);
|
||||
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
|
||||
static uint8_t get_syscfg_mask(reg_gpio_t *port);
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_reset(reg_gpio_t *port)
|
||||
{
|
||||
if(port == GPIOA) {
|
||||
/* Reset GPIOA specific values */
|
||||
port->MODER = 0xa8000000;
|
||||
port->OSPEEDR = 0x00000000;
|
||||
port->PUPDR = 0x64000000;
|
||||
}
|
||||
else if (port == GPIOB) {
|
||||
/* Reset GPIOB specific values */
|
||||
port->MODER = 0x00000280;
|
||||
port->OSPEEDR = 0x000000c0;
|
||||
port->PUPDR = 0x00000100;
|
||||
} else {
|
||||
/* Reset other GPIO */
|
||||
port->MODER = 0x00000000;
|
||||
port->OSPEEDR = 0x00000000;
|
||||
port->PUPDR = 0x00000000;
|
||||
}
|
||||
|
||||
port->OTYPER = 0x00000000;
|
||||
port->AFRL = 0x00000000;
|
||||
port->AFRH = 0x00000000;
|
||||
port->ODR = 0x00000000;
|
||||
}
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
init.pins = intercept_overwrite_register(port, init.pins);
|
||||
|
||||
/* process mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
|
||||
|
||||
/* process pull up/down resitors */
|
||||
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
|
||||
{
|
||||
/* treat like input */
|
||||
hal_gpio_init_input(port, init);
|
||||
|
||||
/* change mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
init.pins = intercept_overwrite_register(port, init.pins);
|
||||
|
||||
/* process mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
|
||||
|
||||
/* process pull up/down resitors */
|
||||
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
|
||||
|
||||
/* process port speed */
|
||||
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
|
||||
|
||||
/* process output typ */
|
||||
port->OTYPER &= ~init.pins;
|
||||
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
|
||||
port->OTYPER |= init.pins;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_alternate(reg_gpio_t *port,
|
||||
hal_gpio_af_t af_mode,
|
||||
hal_gpio_output_t init)
|
||||
{
|
||||
/* treat like output */
|
||||
hal_gpio_init_output(port, init);
|
||||
|
||||
/* change mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
|
||||
|
||||
/* process af type */
|
||||
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
|
||||
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
|
||||
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
|
||||
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
uint16_t hal_gpio_input_read(reg_gpio_t *port)
|
||||
{
|
||||
return (uint16_t) port->IDR;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
uint16_t hal_gpio_output_read(reg_gpio_t *port)
|
||||
{
|
||||
return (uint16_t) port->ODR;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
port_value = intercept_overwrite_register(port, port_value);
|
||||
port->ODR = port_value;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
port->BSRR = pins;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
port->BSRR = (pins << 16);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
uint16_t pattern;
|
||||
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
/* get actual value and invert */
|
||||
pattern = hal_gpio_output_read(port);
|
||||
pattern = ~pattern;
|
||||
|
||||
/* mask pins */
|
||||
pattern &= pins;
|
||||
|
||||
port->ODR = pattern;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_irq_set(reg_gpio_t *port,
|
||||
uint16_t pins,
|
||||
hal_gpio_trg_t edge,
|
||||
hal_bool_t status)
|
||||
{
|
||||
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
|
||||
uint32_t exticr_mask;
|
||||
|
||||
for (exti_line = 0u; exti_line < 16u; exti_line++) {
|
||||
if (pins & (0x1 << exti_line)) {
|
||||
syscfg_bank = exti_line / 4u;
|
||||
syscfg_shift = exti_line % 4u;
|
||||
nvic_bank = (exti_line < 10u) ? 0u : 1u;
|
||||
|
||||
if (status == ENABLE) {
|
||||
/* Trigger (rising/falling/both) */
|
||||
if (edge & HAL_GPIO_TRG_POS) {
|
||||
EXTI->RTSR |= (0x1 << exti_line);
|
||||
}
|
||||
if (edge & HAL_GPIO_TRG_NEG) {
|
||||
EXTI->FTSR |= (0x1 << exti_line);
|
||||
}
|
||||
/* Set EXTI line to corresponding GPIO port */
|
||||
exticr_mask = get_syscfg_mask(port);
|
||||
if (syscfg_bank == 0u) {
|
||||
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 1u) {
|
||||
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 2u) {
|
||||
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 3u) {
|
||||
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
|
||||
}
|
||||
|
||||
/* Unmask interrupt */
|
||||
EXTI->IMR |= (0x1 << exti_line);
|
||||
if (nvic_bank == 0u) {
|
||||
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 1u) {
|
||||
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 2u) {
|
||||
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Mask interrupt */
|
||||
EXTI->IMR &= ~(0x1 << exti_line);
|
||||
if (nvic_bank == 0u) {
|
||||
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 1u) {
|
||||
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 2u) {
|
||||
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_gpio_irq_status(uint16_t pin)
|
||||
{
|
||||
hal_bool_t status = DISABLED;
|
||||
|
||||
if ((EXTI->IMR && pin) &&
|
||||
(EXTI->PR && pin)) {
|
||||
status = ENABLED;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_irq_clear(uint16_t pin)
|
||||
{
|
||||
EXTI->PR |= pin;
|
||||
}
|
||||
|
||||
|
||||
/* -- Local function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Creates a pattern based on specified pins.
|
||||
*
|
||||
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
|
||||
* ==> pattern = 0x0000'0288
|
||||
*
|
||||
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
|
||||
* ^ ^ ^
|
||||
* ==> 0b0..0'00010'1000'1000
|
||||
* ^^ ^^ ^^
|
||||
*
|
||||
* pattern_bit_width must be 2 or 4
|
||||
*/
|
||||
static uint32_t create_pattern_mask(uint16_t pins,
|
||||
uint8_t pattern,
|
||||
uint8_t pattern_bit_width)
|
||||
{
|
||||
const uint8_t mask_bit_width = 32u;
|
||||
const uint16_t pin1_mask = 1u;
|
||||
|
||||
uint8_t pos, end;
|
||||
uint32_t mask = 0u;
|
||||
|
||||
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
|
||||
/* create pattern mask */
|
||||
end = mask_bit_width / pattern_bit_width;
|
||||
for (pos = 0; pos < end; pos++) {
|
||||
if (pins & pin1_mask) {
|
||||
mask |= pattern << (pos * pattern_bit_width);
|
||||
}
|
||||
pins >>= 1;
|
||||
}
|
||||
} else {
|
||||
/* exit if pattern_bit_width not as needed */
|
||||
mask = 0u;
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief This function ensures that these sensitive pins are not reconfigured.
|
||||
*
|
||||
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
|
||||
* Pins 15 down to 12 are used for system functions of the discovery board,
|
||||
* e.g. connection of the debugger.
|
||||
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
|
||||
*/
|
||||
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
|
||||
if (port == GPIOA || port == GPIOB){
|
||||
pins &= 0x0FFF;
|
||||
}
|
||||
return pins;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
|
||||
* \param port : Port of which the mask should be generated.
|
||||
* \return Mask for specified port.
|
||||
*/
|
||||
static uint8_t get_syscfg_mask(reg_gpio_t *port)
|
||||
{
|
||||
return ((port == GPIOA) ? 0u :
|
||||
(port == GPIOB) ? 1u :
|
||||
(port == GPIOC) ? 2u :
|
||||
(port == GPIOD) ? 3u :
|
||||
(port == GPIOE) ? 4u :
|
||||
(port == GPIOF) ? 5u :
|
||||
(port == GPIOG) ? 6u :
|
||||
(port == GPIOH) ? 7u :
|
||||
(port == GPIOI) ? 8u :
|
||||
(port == GPIOJ) ? 9u : 10u);
|
||||
}
|
||||
@@ -0,0 +1,132 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_pwr.
|
||||
*
|
||||
* The hardware abstraction layer for the power control unit.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_pwr.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define TIME_OUT 0x1000
|
||||
#define MASK_PERIPH_PWR (1u << 28u)
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_reset(void)
|
||||
{
|
||||
/* Reset peripheral */
|
||||
PWR->CR = 0x0000c000;
|
||||
PWR->CSR = 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
uint32_t reg = 0;
|
||||
|
||||
if (status == DISABLE) {
|
||||
/* Disable backup domain / regulator */
|
||||
PWR->CSR &= ~(1u << 9u);
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
/* Enable backup domain / regulator */
|
||||
PWR->CSR |= (1u << 9u);
|
||||
|
||||
/* Wait till regulator is ready and if time out is reached exit */
|
||||
reg = PWR->CSR & (1u << 3u);
|
||||
while ((reg == 0) && (count != TIME_OUT)) {
|
||||
reg = PWR->CSR & (1u << 3u);
|
||||
count++;
|
||||
}
|
||||
|
||||
/* Return */
|
||||
if (reg != 0) {
|
||||
return ENABLED;
|
||||
}
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_backup_access(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CR &= ~(1u << 8u);
|
||||
} else {
|
||||
PWR->CR |= (1u << 8u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_wakeup_pin(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CSR &= ~(1u << 8u);
|
||||
} else {
|
||||
PWR->CSR |= (1u << 8u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_flash_powerdown(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CR &= ~(1u << 9u);
|
||||
} else {
|
||||
PWR->CR |= (1u << 9u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
|
||||
{
|
||||
/* Is this realy nedded ?
|
||||
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
|
||||
{
|
||||
/* Is this realy nedded ? */
|
||||
return DISABLED;
|
||||
}
|
||||
@@ -0,0 +1,347 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_rcc.
|
||||
*
|
||||
* The hardware abstraction layer for the reset and clock control unit.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_rcc.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define TIME_OUT 0x5000
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_reset(void)
|
||||
{
|
||||
/* Set RCC->CR to default values */
|
||||
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
|
||||
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
|
||||
// PLLSAI bits (STM32F42xx/43xx)
|
||||
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
|
||||
|
||||
/* Reset RCC->CFGR to default values */
|
||||
RCC->CFGR = 0u;
|
||||
|
||||
/* Reset RCC->PLLxCFGR to default values */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
RCC->PLLI2SCFGR = 0x20003000;
|
||||
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0u;
|
||||
|
||||
/* Disable all peripherals */
|
||||
RCC->AHB1RSTR = 0u;
|
||||
RCC->AHB2RSTR = 0u;
|
||||
RCC->AHB3RSTR = 0u;
|
||||
RCC->APB1RSTR = 0u;
|
||||
RCC->APB2RSTR = 0u;
|
||||
RCC->AHB1ENR = 0x00100000;
|
||||
RCC->AHB2ENR = 0u;
|
||||
RCC->AHB3ENR = 0u;
|
||||
RCC->APB1ENR = 0u;
|
||||
RCC->APB2ENR = 0u;
|
||||
RCC->AHB1LPENR = 0x7e6791ff;
|
||||
RCC->AHB2LPENR = 0x000000f1;
|
||||
RCC->AHB3LPENR = 0x00000001;
|
||||
RCC->APB1LPENR = 0x36fec9ff;
|
||||
RCC->APB2LPENR = 0x00075f33;
|
||||
|
||||
/* Reset forgotten registers */
|
||||
RCC->BDCR = 0u;
|
||||
RCC->CSR = 0x0e000000;
|
||||
RCC->SSCGR = 0u;
|
||||
RCC->DCKCFGR = 0u;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
|
||||
{
|
||||
volatile uint32_t *reg;
|
||||
uint32_t bit_pos;
|
||||
|
||||
/* Select correct enable register */
|
||||
switch (peripheral) {
|
||||
/* AHB1 */
|
||||
case PER_GPIOA:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOB:
|
||||
bit_pos = 1u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOC:
|
||||
bit_pos = 2u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOD:
|
||||
bit_pos = 3u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOE:
|
||||
bit_pos = 4u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOF:
|
||||
bit_pos = 5u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOG:
|
||||
bit_pos = 6u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOH:
|
||||
bit_pos = 7u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOI:
|
||||
bit_pos = 8u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOJ:
|
||||
bit_pos = 9u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOK:
|
||||
bit_pos = 10u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_DMA1:
|
||||
bit_pos = 21u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_DMA2:
|
||||
bit_pos = 22u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
|
||||
/* AHB3 */
|
||||
case PER_FMC:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->AHB3ENR;
|
||||
break;
|
||||
|
||||
/* APB1 */
|
||||
case PER_DAC:
|
||||
bit_pos = 29u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_PWR:
|
||||
bit_pos = 28u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM2:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM3:
|
||||
bit_pos = 1u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM4:
|
||||
bit_pos = 2u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM5:
|
||||
bit_pos = 3u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
|
||||
|
||||
/* APB2 */
|
||||
case PER_ADC1:
|
||||
bit_pos = 8u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
case PER_ADC2:
|
||||
bit_pos = 9u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
case PER_ADC3:
|
||||
bit_pos = 10u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (status == DISABLE) {
|
||||
*reg &= ~(1u << bit_pos);
|
||||
} else {
|
||||
*reg |= (1u << bit_pos);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
uint32_t count = 0;
|
||||
|
||||
/* Disable source */
|
||||
if (status == DISABLE) {
|
||||
RCC->CR &= ~(1u << source);
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
/* If pll, check if source is ok */
|
||||
if (source == HAL_RCC_OSC_PLL ||
|
||||
source == HAL_RCC_OSC_PLLI2S ||
|
||||
source == HAL_RCC_OSC_PLLSAI)
|
||||
{
|
||||
reg = RCC->CR;
|
||||
/* HSE */
|
||||
if (RCC->PLLCFGR & ~(1u << 22u)) {
|
||||
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
|
||||
}
|
||||
/* HSI */
|
||||
else {
|
||||
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
|
||||
}
|
||||
/* Return if source is not ok */
|
||||
if (!reg) {
|
||||
return DISABLED;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable source */
|
||||
RCC->CR |= (1u << source);
|
||||
|
||||
/* Wait till source is ready and if time out is reached exit */
|
||||
reg = RCC->CR & (1u << (source + 1u));
|
||||
while ((reg == 0) && (count != TIME_OUT)) {
|
||||
reg = RCC->CR & (1u << (source + 1u));
|
||||
count++;
|
||||
}
|
||||
|
||||
/* Return */
|
||||
if (reg != 0) {
|
||||
return ENABLED;
|
||||
}
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
|
||||
{
|
||||
/* Input check */
|
||||
if (init.m_divider < 2u) init.m_divider = 2u;
|
||||
|
||||
if (init.n_factor < 2u) init.n_factor = 2u;
|
||||
if (init.n_factor > 432u) init.n_factor = 432u;
|
||||
|
||||
if (init.p_divider > 8u) init.p_divider = 8u;
|
||||
|
||||
if (init.q_divider < 2u) init.q_divider = 2u;
|
||||
|
||||
init.r_divider &= 0x07;
|
||||
|
||||
/* Set source or return if invalid */
|
||||
if (init.source == HAL_RCC_OSC_HSI) {
|
||||
RCC->PLLCFGR &= ~(1u << 22u);
|
||||
} else if (init.source == HAL_RCC_OSC_HSE) {
|
||||
RCC->PLLCFGR |= (1u << 22u);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set pll preescaler */
|
||||
RCC->PLLCFGR &= ~(0x3f);
|
||||
RCC->PLLCFGR |= init.m_divider;
|
||||
|
||||
/* Configure pll */
|
||||
switch (pll) {
|
||||
case HAL_RCC_OSC_PLL:
|
||||
RCC->PLLCFGR &= ~0x0f037fc0;
|
||||
RCC->PLLCFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
|
||||
RCC->PLLCFGR |= (init.q_divider << 24u);
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_PLLI2S:
|
||||
RCC->PLLI2SCFGR &= ~0x7f007fc0;
|
||||
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
|
||||
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
|
||||
break;
|
||||
|
||||
/* case HAL_RCC_OSC_PLLSAI:
|
||||
RCC->PLLSAICFGR &= ~0x7f007fc0;
|
||||
RCC->PLLSAICFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLSAICFGR |= (init.q_divider << 24u);
|
||||
RCC->PLLSAICFGR |= (init.r_divider << 28u);
|
||||
break;
|
||||
*/
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
/* Configure clock divider */
|
||||
RCC->CFGR &= ~0x0000fcf0;
|
||||
RCC->CFGR |= (init.hpre << 4u);
|
||||
RCC->CFGR |= (init.ppre1 << 10u);
|
||||
RCC->CFGR |= (init.ppre2 << 13u);
|
||||
|
||||
/* Select system clock source */
|
||||
RCC->CFGR &= ~0x00000003;
|
||||
switch (init.osc) {
|
||||
default:
|
||||
case HAL_RCC_OSC_HSI:
|
||||
reg = 0u;
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_HSE:
|
||||
reg = 1u;
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_PLL:
|
||||
reg = 2u;
|
||||
break;
|
||||
}
|
||||
RCC->CFGR |= reg;
|
||||
|
||||
#ifndef TESTING
|
||||
/* Wait till system clock is selected */
|
||||
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,143 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_fmc.
|
||||
*
|
||||
* The hardware abstraction layer for the memory controller.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_fmc.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define MASK_PERIPH_FMC (0x00000001)
|
||||
#define MASK_SRAM_ENABLE (0x00000001)
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_fmc_reset(hal_fmc_bank_t bank)
|
||||
{
|
||||
switch (bank) {
|
||||
default:
|
||||
case HAL_FMC_SRAM_BANK1:
|
||||
FMC->SRAM.BCR1 = 0x000030db;
|
||||
FMC->SRAM.BTR1 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK2:
|
||||
FMC->SRAM.BCR2 = 0x000030d2;
|
||||
FMC->SRAM.BTR2 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK3:
|
||||
FMC->SRAM.BCR3 = 0x000030d2;
|
||||
FMC->SRAM.BTR3 = 0x0fffffff;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK4:
|
||||
FMC->SRAM.BCR4 = 0x000030d2;
|
||||
FMC->SRAM.BTR4 = 0x0fffffff;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_fmc_init_sram(hal_fmc_bank_t bank,
|
||||
hal_fmc_sram_init_t init,
|
||||
hal_fmc_sram_timing_t timing)
|
||||
{
|
||||
uint32_t reg_cr = 0, reg_tr = 0;
|
||||
|
||||
/* Input check */
|
||||
timing.address_setup &= 0xf;
|
||||
timing.address_hold &= 0xf;
|
||||
if (timing.address_hold < 1u) timing.address_hold = 1u;
|
||||
timing.data_setup &= 0xff;
|
||||
if (timing.data_setup < 1u) timing.data_setup = 1u;
|
||||
timing.bus_turnaround &= 0xf;
|
||||
|
||||
/* Input check clock divider (2..16) */
|
||||
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
|
||||
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
|
||||
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
|
||||
|
||||
/* Input check data latency (2..17) */
|
||||
if (timing.data_latency > 17u) timing.data_latency = 17u;
|
||||
if (timing.data_latency < 2u) timing.data_latency = 2u;
|
||||
timing.data_latency -= 2u; // 0b0000 -> latency = 2
|
||||
|
||||
/* Process boolean parameter */
|
||||
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
|
||||
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
|
||||
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
|
||||
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
|
||||
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
|
||||
|
||||
/* Process non boolean parameter */
|
||||
reg_cr |= (init.type << 2u);
|
||||
reg_cr |= (init.width << 4u);
|
||||
|
||||
/* Process timing for async. SRAM */
|
||||
if (init.type == HAL_FMC_TYPE_SRAM) {
|
||||
reg_tr |= (timing.address_setup << 0u);
|
||||
reg_tr |= (timing.address_hold << 4u);
|
||||
reg_tr |= (timing.data_setup << 8u);
|
||||
reg_tr |= (timing.mode << 28u);
|
||||
}
|
||||
/* Process timing for sync. PSRAM */
|
||||
else if (init.type == HAL_FMC_TYPE_PSRAM) {
|
||||
reg_tr |= (timing.clk_divider << 20u);
|
||||
reg_tr |= (timing.data_latency << 24u);
|
||||
}
|
||||
/* Process bus turnaround time */
|
||||
reg_tr |= (timing.bus_turnaround << 16u);
|
||||
|
||||
/* Write register */
|
||||
switch (bank) {
|
||||
default:
|
||||
case HAL_FMC_SRAM_BANK1:
|
||||
FMC->SRAM.BCR1 = reg_cr;
|
||||
FMC->SRAM.BTR1 = reg_tr;
|
||||
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK2:
|
||||
FMC->SRAM.BCR2 = reg_cr;
|
||||
FMC->SRAM.BTR2 = reg_tr;
|
||||
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK3:
|
||||
FMC->SRAM.BCR3 = reg_cr;
|
||||
FMC->SRAM.BTR3 = reg_tr;
|
||||
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
|
||||
case HAL_FMC_SRAM_BANK4:
|
||||
FMC->SRAM.BCR4 = reg_cr;
|
||||
FMC->SRAM.BTR4 = reg_tr;
|
||||
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,412 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_gpio.
|
||||
*
|
||||
* The hardware abstraction layer for the GPIO periphery.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_gpio.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define NVIC_OFFSET_1_4 ( 6u)
|
||||
#define NVIC_OFFSET_5_9 (23u)
|
||||
#define NVIC_OFFSET_10_15 ( 8u)
|
||||
|
||||
|
||||
/* -- Local function declarations
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
static uint32_t create_pattern_mask(uint16_t pins,
|
||||
uint8_t pattern,
|
||||
uint8_t pattern_bit_width);
|
||||
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
|
||||
static uint8_t get_syscfg_mask(reg_gpio_t *port);
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_reset(reg_gpio_t *port)
|
||||
{
|
||||
if(port == GPIOA) {
|
||||
/* Reset GPIOA specific values */
|
||||
port->MODER = 0xa8000000;
|
||||
port->OSPEEDR = 0x00000000;
|
||||
port->PUPDR = 0x64000000;
|
||||
}
|
||||
else if (port == GPIOB) {
|
||||
/* Reset GPIOB specific values */
|
||||
port->MODER = 0x00000280;
|
||||
port->OSPEEDR = 0x000000c0;
|
||||
port->PUPDR = 0x00000100;
|
||||
} else {
|
||||
/* Reset other GPIO */
|
||||
port->MODER = 0x00000000;
|
||||
port->OSPEEDR = 0x00000000;
|
||||
port->PUPDR = 0x00000000;
|
||||
}
|
||||
|
||||
port->OTYPER = 0x00000000;
|
||||
port->AFRL = 0x00000000;
|
||||
port->AFRH = 0x00000000;
|
||||
port->ODR = 0x00000000;
|
||||
}
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
init.pins = intercept_overwrite_register(port, init.pins);
|
||||
|
||||
/* process mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
|
||||
|
||||
/* process pull up/down resitors */
|
||||
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
|
||||
{
|
||||
/* treat like input */
|
||||
hal_gpio_init_input(port, init);
|
||||
|
||||
/* change mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
init.pins = intercept_overwrite_register(port, init.pins);
|
||||
|
||||
/* process mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
|
||||
|
||||
/* process pull up/down resitors */
|
||||
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
|
||||
|
||||
/* process port speed */
|
||||
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
|
||||
|
||||
/* process output typ */
|
||||
port->OTYPER &= ~init.pins;
|
||||
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
|
||||
port->OTYPER |= init.pins;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_init_alternate(reg_gpio_t *port,
|
||||
hal_gpio_af_t af_mode,
|
||||
hal_gpio_output_t init)
|
||||
{
|
||||
/* treat like output */
|
||||
hal_gpio_init_output(port, init);
|
||||
|
||||
/* change mode */
|
||||
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
|
||||
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
|
||||
|
||||
/* process af type */
|
||||
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
|
||||
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
|
||||
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
|
||||
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
uint16_t hal_gpio_input_read(reg_gpio_t *port)
|
||||
{
|
||||
return (uint16_t) port->IDR;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
uint16_t hal_gpio_output_read(reg_gpio_t *port)
|
||||
{
|
||||
return (uint16_t) port->ODR;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
port_value = intercept_overwrite_register(port, port_value);
|
||||
port->ODR = port_value;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
port->BSRR = pins;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
port->BSRR = (pins << 16);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
|
||||
{
|
||||
uint16_t pattern;
|
||||
|
||||
/* prevent overwrite false reg entry */
|
||||
pins = intercept_overwrite_register(port, pins);
|
||||
|
||||
/* exit if no pins to be configured */
|
||||
if (pins != 0) {
|
||||
/* get actual value and invert */
|
||||
pattern = hal_gpio_output_read(port);
|
||||
pattern = ~pattern;
|
||||
|
||||
/* mask pins */
|
||||
pattern &= pins;
|
||||
|
||||
port->ODR = pattern;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_irq_set(reg_gpio_t *port,
|
||||
uint16_t pins,
|
||||
hal_gpio_trg_t edge,
|
||||
hal_bool_t status)
|
||||
{
|
||||
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
|
||||
uint32_t exticr_mask;
|
||||
|
||||
for (exti_line = 0u; exti_line < 16u; exti_line++) {
|
||||
if (pins & (0x1 << exti_line)) {
|
||||
syscfg_bank = exti_line / 4u;
|
||||
syscfg_shift = exti_line % 4u;
|
||||
nvic_bank = (exti_line < 10u) ? 0u : 1u;
|
||||
|
||||
if (status == ENABLE) {
|
||||
/* Trigger (rising/falling/both) */
|
||||
if (edge & HAL_GPIO_TRG_POS) {
|
||||
EXTI->RTSR |= (0x1 << exti_line);
|
||||
}
|
||||
if (edge & HAL_GPIO_TRG_NEG) {
|
||||
EXTI->FTSR |= (0x1 << exti_line);
|
||||
}
|
||||
/* Set EXTI line to corresponding GPIO port */
|
||||
exticr_mask = get_syscfg_mask(port);
|
||||
if (syscfg_bank == 0u) {
|
||||
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 1u) {
|
||||
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 2u) {
|
||||
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
|
||||
} else if (syscfg_bank == 3u) {
|
||||
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
|
||||
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
|
||||
}
|
||||
|
||||
/* Unmask interrupt */
|
||||
EXTI->IMR |= (0x1 << exti_line);
|
||||
if (nvic_bank == 0u) {
|
||||
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 1u) {
|
||||
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 2u) {
|
||||
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
}
|
||||
|
||||
} else {
|
||||
/* Mask interrupt */
|
||||
EXTI->IMR &= ~(0x1 << exti_line);
|
||||
if (nvic_bank == 0u) {
|
||||
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 1u) {
|
||||
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
} else if (nvic_bank == 2u) {
|
||||
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
|
||||
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_gpio_irq_status(uint16_t pin)
|
||||
{
|
||||
hal_bool_t status = DISABLED;
|
||||
|
||||
if ((EXTI->IMR && pin) &&
|
||||
(EXTI->PR && pin)) {
|
||||
status = ENABLED;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_gpio_irq_clear(uint16_t pin)
|
||||
{
|
||||
EXTI->PR |= pin;
|
||||
}
|
||||
|
||||
|
||||
/* -- Local function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* \brief Creates a pattern based on specified pins.
|
||||
*
|
||||
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
|
||||
* ==> pattern = 0x0000'0288
|
||||
*
|
||||
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
|
||||
* ^ ^ ^
|
||||
* ==> 0b0..0'00010'1000'1000
|
||||
* ^^ ^^ ^^
|
||||
*
|
||||
* pattern_bit_width must be 2 or 4
|
||||
*/
|
||||
static uint32_t create_pattern_mask(uint16_t pins,
|
||||
uint8_t pattern,
|
||||
uint8_t pattern_bit_width)
|
||||
{
|
||||
const uint8_t mask_bit_width = 32u;
|
||||
const uint16_t pin1_mask = 1u;
|
||||
|
||||
uint8_t pos, end;
|
||||
uint32_t mask = 0u;
|
||||
|
||||
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
|
||||
/* create pattern mask */
|
||||
end = mask_bit_width / pattern_bit_width;
|
||||
for (pos = 0; pos < end; pos++) {
|
||||
if (pins & pin1_mask) {
|
||||
mask |= pattern << (pos * pattern_bit_width);
|
||||
}
|
||||
pins >>= 1;
|
||||
}
|
||||
} else {
|
||||
/* exit if pattern_bit_width not as needed */
|
||||
mask = 0u;
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief This function ensures that these sensitive pins are not reconfigured.
|
||||
*
|
||||
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
|
||||
* Pins 15 down to 12 are used for system functions of the discovery board,
|
||||
* e.g. connection of the debugger.
|
||||
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
|
||||
*/
|
||||
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
|
||||
if (port == GPIOA || port == GPIOB){
|
||||
pins &= 0x0FFF;
|
||||
}
|
||||
return pins;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
|
||||
* \param port : Port of which the mask should be generated.
|
||||
* \return Mask for specified port.
|
||||
*/
|
||||
static uint8_t get_syscfg_mask(reg_gpio_t *port)
|
||||
{
|
||||
return ((port == GPIOA) ? 0u :
|
||||
(port == GPIOB) ? 1u :
|
||||
(port == GPIOC) ? 2u :
|
||||
(port == GPIOD) ? 3u :
|
||||
(port == GPIOE) ? 4u :
|
||||
(port == GPIOF) ? 5u :
|
||||
(port == GPIOG) ? 6u :
|
||||
(port == GPIOH) ? 7u :
|
||||
(port == GPIOI) ? 8u :
|
||||
(port == GPIOJ) ? 9u : 10u);
|
||||
}
|
||||
@@ -0,0 +1,132 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_pwr.
|
||||
*
|
||||
* The hardware abstraction layer for the power control unit.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_pwr.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define TIME_OUT 0x1000
|
||||
#define MASK_PERIPH_PWR (1u << 28u)
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_reset(void)
|
||||
{
|
||||
/* Reset peripheral */
|
||||
PWR->CR = 0x0000c000;
|
||||
PWR->CSR = 0x00000000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
uint32_t reg = 0;
|
||||
|
||||
if (status == DISABLE) {
|
||||
/* Disable backup domain / regulator */
|
||||
PWR->CSR &= ~(1u << 9u);
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
/* Enable backup domain / regulator */
|
||||
PWR->CSR |= (1u << 9u);
|
||||
|
||||
/* Wait till regulator is ready and if time out is reached exit */
|
||||
reg = PWR->CSR & (1u << 3u);
|
||||
while ((reg == 0) && (count != TIME_OUT)) {
|
||||
reg = PWR->CSR & (1u << 3u);
|
||||
count++;
|
||||
}
|
||||
|
||||
/* Return */
|
||||
if (reg != 0) {
|
||||
return ENABLED;
|
||||
}
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_backup_access(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CR &= ~(1u << 8u);
|
||||
} else {
|
||||
PWR->CR |= (1u << 8u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_wakeup_pin(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CSR &= ~(1u << 8u);
|
||||
} else {
|
||||
PWR->CSR |= (1u << 8u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_pwr_set_flash_powerdown(hal_bool_t status)
|
||||
{
|
||||
if (status == DISABLE) {
|
||||
PWR->CR &= ~(1u << 9u);
|
||||
} else {
|
||||
PWR->CR |= (1u << 9u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
|
||||
{
|
||||
/* Is this realy nedded ?
|
||||
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
|
||||
{
|
||||
/* Is this realy nedded ? */
|
||||
return DISABLED;
|
||||
}
|
||||
@@ -0,0 +1,347 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -- _____ ______ _____ -
|
||||
* -- |_ _| | ____|/ ____| -
|
||||
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
|
||||
* -- | | | '_ \| __| \___ \ Zurich University of -
|
||||
* -- _| |_| | | | |____ ____) | Applied Sciences -
|
||||
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
|
||||
* ------------------------------------------------------------------------- */
|
||||
/**
|
||||
* \brief Implementation of module hal_rcc.
|
||||
*
|
||||
* The hardware abstraction layer for the reset and clock control unit.
|
||||
*
|
||||
* $Id$
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* User includes */
|
||||
#include "hal_rcc.h"
|
||||
#include "reg_stm32f4xx.h"
|
||||
|
||||
|
||||
/* -- Macros
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define TIME_OUT 0x5000
|
||||
|
||||
|
||||
/* -- Public function definitions
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_reset(void)
|
||||
{
|
||||
/* Set RCC->CR to default values */
|
||||
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
|
||||
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
|
||||
// PLLSAI bits (STM32F42xx/43xx)
|
||||
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
|
||||
|
||||
/* Reset RCC->CFGR to default values */
|
||||
RCC->CFGR = 0u;
|
||||
|
||||
/* Reset RCC->PLLxCFGR to default values */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
RCC->PLLI2SCFGR = 0x20003000;
|
||||
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0u;
|
||||
|
||||
/* Disable all peripherals */
|
||||
RCC->AHB1RSTR = 0u;
|
||||
RCC->AHB2RSTR = 0u;
|
||||
RCC->AHB3RSTR = 0u;
|
||||
RCC->APB1RSTR = 0u;
|
||||
RCC->APB2RSTR = 0u;
|
||||
RCC->AHB1ENR = 0x00100000;
|
||||
RCC->AHB2ENR = 0u;
|
||||
RCC->AHB3ENR = 0u;
|
||||
RCC->APB1ENR = 0u;
|
||||
RCC->APB2ENR = 0u;
|
||||
RCC->AHB1LPENR = 0x7e6791ff;
|
||||
RCC->AHB2LPENR = 0x000000f1;
|
||||
RCC->AHB3LPENR = 0x00000001;
|
||||
RCC->APB1LPENR = 0x36fec9ff;
|
||||
RCC->APB2LPENR = 0x00075f33;
|
||||
|
||||
/* Reset forgotten registers */
|
||||
RCC->BDCR = 0u;
|
||||
RCC->CSR = 0x0e000000;
|
||||
RCC->SSCGR = 0u;
|
||||
RCC->DCKCFGR = 0u;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
|
||||
{
|
||||
volatile uint32_t *reg;
|
||||
uint32_t bit_pos;
|
||||
|
||||
/* Select correct enable register */
|
||||
switch (peripheral) {
|
||||
/* AHB1 */
|
||||
case PER_GPIOA:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOB:
|
||||
bit_pos = 1u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOC:
|
||||
bit_pos = 2u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOD:
|
||||
bit_pos = 3u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOE:
|
||||
bit_pos = 4u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOF:
|
||||
bit_pos = 5u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOG:
|
||||
bit_pos = 6u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOH:
|
||||
bit_pos = 7u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOI:
|
||||
bit_pos = 8u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOJ:
|
||||
bit_pos = 9u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_GPIOK:
|
||||
bit_pos = 10u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_DMA1:
|
||||
bit_pos = 21u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
case PER_DMA2:
|
||||
bit_pos = 22u;
|
||||
reg = &RCC->AHB1ENR;
|
||||
break;
|
||||
|
||||
/* AHB3 */
|
||||
case PER_FMC:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->AHB3ENR;
|
||||
break;
|
||||
|
||||
/* APB1 */
|
||||
case PER_DAC:
|
||||
bit_pos = 29u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_PWR:
|
||||
bit_pos = 28u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM2:
|
||||
bit_pos = 0u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM3:
|
||||
bit_pos = 1u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM4:
|
||||
bit_pos = 2u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
case PER_TIM5:
|
||||
bit_pos = 3u;
|
||||
reg = &RCC->APB1ENR;
|
||||
break;
|
||||
|
||||
|
||||
/* APB2 */
|
||||
case PER_ADC1:
|
||||
bit_pos = 8u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
case PER_ADC2:
|
||||
bit_pos = 9u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
case PER_ADC3:
|
||||
bit_pos = 10u;
|
||||
reg = &RCC->APB2ENR;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (status == DISABLE) {
|
||||
*reg &= ~(1u << bit_pos);
|
||||
} else {
|
||||
*reg |= (1u << bit_pos);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
uint32_t count = 0;
|
||||
|
||||
/* Disable source */
|
||||
if (status == DISABLE) {
|
||||
RCC->CR &= ~(1u << source);
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
/* If pll, check if source is ok */
|
||||
if (source == HAL_RCC_OSC_PLL ||
|
||||
source == HAL_RCC_OSC_PLLI2S ||
|
||||
source == HAL_RCC_OSC_PLLSAI)
|
||||
{
|
||||
reg = RCC->CR;
|
||||
/* HSE */
|
||||
if (RCC->PLLCFGR & ~(1u << 22u)) {
|
||||
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
|
||||
}
|
||||
/* HSI */
|
||||
else {
|
||||
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
|
||||
}
|
||||
/* Return if source is not ok */
|
||||
if (!reg) {
|
||||
return DISABLED;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable source */
|
||||
RCC->CR |= (1u << source);
|
||||
|
||||
/* Wait till source is ready and if time out is reached exit */
|
||||
reg = RCC->CR & (1u << (source + 1u));
|
||||
while ((reg == 0) && (count != TIME_OUT)) {
|
||||
reg = RCC->CR & (1u << (source + 1u));
|
||||
count++;
|
||||
}
|
||||
|
||||
/* Return */
|
||||
if (reg != 0) {
|
||||
return ENABLED;
|
||||
}
|
||||
return DISABLED;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
|
||||
{
|
||||
/* Input check */
|
||||
if (init.m_divider < 2u) init.m_divider = 2u;
|
||||
|
||||
if (init.n_factor < 2u) init.n_factor = 2u;
|
||||
if (init.n_factor > 432u) init.n_factor = 432u;
|
||||
|
||||
if (init.p_divider > 8u) init.p_divider = 8u;
|
||||
|
||||
if (init.q_divider < 2u) init.q_divider = 2u;
|
||||
|
||||
init.r_divider &= 0x07;
|
||||
|
||||
/* Set source or return if invalid */
|
||||
if (init.source == HAL_RCC_OSC_HSI) {
|
||||
RCC->PLLCFGR &= ~(1u << 22u);
|
||||
} else if (init.source == HAL_RCC_OSC_HSE) {
|
||||
RCC->PLLCFGR |= (1u << 22u);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set pll preescaler */
|
||||
RCC->PLLCFGR &= ~(0x3f);
|
||||
RCC->PLLCFGR |= init.m_divider;
|
||||
|
||||
/* Configure pll */
|
||||
switch (pll) {
|
||||
case HAL_RCC_OSC_PLL:
|
||||
RCC->PLLCFGR &= ~0x0f037fc0;
|
||||
RCC->PLLCFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
|
||||
RCC->PLLCFGR |= (init.q_divider << 24u);
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_PLLI2S:
|
||||
RCC->PLLI2SCFGR &= ~0x7f007fc0;
|
||||
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
|
||||
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
|
||||
break;
|
||||
|
||||
/* case HAL_RCC_OSC_PLLSAI:
|
||||
RCC->PLLSAICFGR &= ~0x7f007fc0;
|
||||
RCC->PLLSAICFGR |= (init.n_factor << 6u);
|
||||
RCC->PLLSAICFGR |= (init.q_divider << 24u);
|
||||
RCC->PLLSAICFGR |= (init.r_divider << 28u);
|
||||
break;
|
||||
*/
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* See header file
|
||||
*/
|
||||
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
/* Configure clock divider */
|
||||
RCC->CFGR &= ~0x0000fcf0;
|
||||
RCC->CFGR |= (init.hpre << 4u);
|
||||
RCC->CFGR |= (init.ppre1 << 10u);
|
||||
RCC->CFGR |= (init.ppre2 << 13u);
|
||||
|
||||
/* Select system clock source */
|
||||
RCC->CFGR &= ~0x00000003;
|
||||
switch (init.osc) {
|
||||
default:
|
||||
case HAL_RCC_OSC_HSI:
|
||||
reg = 0u;
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_HSE:
|
||||
reg = 1u;
|
||||
break;
|
||||
|
||||
case HAL_RCC_OSC_PLL:
|
||||
reg = 2u;
|
||||
break;
|
||||
}
|
||||
RCC->CFGR |= reg;
|
||||
|
||||
#ifndef TESTING
|
||||
/* Wait till system clock is selected */
|
||||
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'strukt_code'
|
||||
* Target: 'Target 1'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
Reference in New Issue
Block a user