commit 95886b12ec5a7fa5cf62064e850416d614929043 Author: Schrom01 Date: Fri Sep 30 07:48:14 2022 +0200 finished Task diff --git a/CT-Lab1-Project/CT-Lab1-Project.uvguix.roman b/CT-Lab1-Project/CT-Lab1-Project.uvguix.roman new file mode 100644 index 0000000..3028dba --- /dev/null +++ b/CT-Lab1-Project/CT-Lab1-Project.uvguix.roman @@ -0,0 +1,3637 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
+ + + C:\Users\roman\Documents\CT-Lab1-Project\app + + + + + + + 38003 + Registers + 140 100 + + + 346 + Code Coverage + 1010 656 + + + 204 + Performance Analyzer + 1170 175 175 496 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 80 80 80 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 166 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 3 + + -32000 + -32000 + + + -1 + -1 + + + 52 + 52 + 1492 + 811 + + + + 0 + + 461 + 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000003000000000000000100000033433A5C55736572735C726F6D616E5C446F63756D656E74735C43542D4C6162312D50726F6A6563745C6170705C7461736B2E6300000000067461736B2E6300000000C5D4F200FFFFFFFF56433A5C55736572735C726F6D616E5C446F63756D656E74735C43542D4C6162312D50726F6A6563745C5254455C4465766963655C43545F426F6172645F485331345F4D305C737461727475705F6374626F6172642E730000000011737461727475705F6374626F6172642E7300000000FFDC7800FFFFFFFF3C433A5C55736572735C726F6D616E5C446F63756D656E74735C43542D4C6162312D50726F6A6563745C6170705C7574696C735F6374626F6172642E68000000000F7574696C735F6374626F6172642E6800000000BECEA100FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000F40000006600000080070000FE020000 + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F40000004F00000090050000DF000000 + + + 16 + F40000006600000090050000F6000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000CE020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000CE020000 + + + 16 + F2000000090100000E02000049030000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000CE020000 + + + 16 + F2000000090100000E02000049030000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000CE020000 + + + 16 + F2000000090100000E02000049030000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 00000000FF02000080070000E6030000 + + + 16 + F200000009010000BA03000099010000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000001902000090050000BD020000 + + + 16 + F200000009010000BA03000099010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000020300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000CE020000 + + + 16 + F2000000090100000E02000049030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000020300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000020300007D070000CD030000 + + + 16 + F2000000090100000E02000049030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000020300007D070000CD030000 + + + 16 + F2000000090100000E02000049030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000020300007D070000CD030000 + + + 16 + F2000000090100000E02000049030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000008D050000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000E603000080070000F9030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000300200008D050000A4020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 3312 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFF4000000DF00000090050000E3000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000F40000006600000090050000F6000000F40000004F00000090050000DF0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF9C0400004F000000A004000029020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000A0040000660000009005000040020000A00400004F000000900500002902000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFF00000004F000000F4000000E7020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000F0000000FE020000000000004F000000F0000000E70200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000015020000900500001902000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000000000000000000003002000090050000D4020000000000001902000090050000BD02000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFC802000019020000CC020000BD02000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF00000000E702000080070000EB020000010000000100001004000000010000006CFEFFFFF8010000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000000000000203000080070000FD03000000000000EB02000080070000E60300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2537 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000000460000000000000000000000000000000001000000010000000180FE880000000000004500000000000000000000000000000000010000000100000001800B810000000000001300000000000000000000000000000000010000000100000001800C810000000000001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050FFFFFFFF0096000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020000001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 976 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1920 + 1080 + + + + 1 + Debug + + -1 + -1 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F40000004F00000080070000DF000000 + + + 16 + F40000006600000080070000F6000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000E2020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 109 + 109 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000E2020000 + + + 16 + F2000000090100000E02000049030000 + + + + 1465 + 1465 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 1935 + 1935 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 195 + 195 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000E2020000 + + + 16 + F2000000090100000E02000049030000 + + + + 196 + 196 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000E2020000 + + + 16 + F2000000090100000E02000049030000 + + + + 197 + 197 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 198 + 198 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 00000000FF020000C0030000E6030000 + + + 16 + F200000009010000BA03000099010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 203 + 203 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + F40000006300000080070000DF000000 + + + 16 + F200000009010000BA03000099010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000BA03000099010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 38003 + 38003 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000ED000000E2020000 + + + 16 + F2000000090100000E02000049030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F200000009010000BA03000099010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F2000000090100000E02000049030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F2000000090100000E02000049030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000440200008D050000A4020000 + + + 16 + F2000000090100000E02000049030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + F7000000660000007D070000C6000000 + + + 16 + F200000009010000BA03000099010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + A3040000660000008D05000010020000 + + + 16 + F200000009010000E2010000D4010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000E603000080070000F9030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 0 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 1 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 000000001C0000006F02000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7030000160300007D070000CD030000 + + + 16 + F200000009010000E2010000D4010000 + + + + 3311 + 000000000B000000000000000020000001000000FFFFFFFFFFFFFFFFF4000000DF00000080070000E3000000010000000100001004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000001000000F40000006600000080070000F6000000F40000004F00000080070000DF0000000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF9C0400004F000000A004000029020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000A0040000660000009005000040020000A00400004F000000900500002902000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFF00000004F000000F4000000FB020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000F000000012030000000000004F000000F0000000FB0200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF04000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF00000000FB02000080070000FF02000001000000010000100400000001000000AAFDFFFF3F00000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000001000000C40300001603000080070000FD030000C4030000FF02000080070000E603000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF000000000000000001000000000000000100000001000000FFFFFFFFC0030000FF020000C4030000E603000001000000020000100400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000000000000FFFFFFFFFFFFFFFF0000000029020000900500002D020000000000000100000004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000000000000000000004402000090050000D4020000000000002D02000090050000BD0200000000000040820046060000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2537 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000004000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000004000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000004000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050FFFFFFFF0096000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000004001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000100150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 955 + 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2362 + 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 0 + + .\app\task.c + 6 + 18 + 28 + 1 + + 0 + + + RTE/Device/CT_Board_HS14_M0/startup_ctboard.s + 0 + 184 + 196 + 1 + + 0 + + + app\utils_ctboard.h + 0 + 1 + 1 + 1 + + 0 + + + + + diff --git a/CT-Lab1-Project/CT-Lab1-Project.uvoptx b/CT-Lab1-Project/CT-Lab1-Project.uvoptx new file mode 100644 index 0000000..db953fc --- /dev/null +++ b/CT-Lab1-Project/CT-Lab1-Project.uvoptx @@ -0,0 +1,245 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_2048 -FL0200000 -FS08000000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 1 + 0 + 0 + .\app\utils_ctboard.c + utils_ctboard.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\app\task.c + task.c + 0 + 0 + + + + + ::Device + 1 + 0 + 0 + 1 + + + + ::HAL + 1 + 0 + 0 + 1 + + + diff --git a/CT-Lab1-Project/CT-Lab1-Project.uvprojx b/CT-Lab1-Project/CT-Lab1-Project.uvprojx new file mode 100644 index 0000000..fecd688 --- /dev/null +++ b/CT-Lab1-Project/CT-Lab1-Project.uvprojx @@ -0,0 +1,503 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6180000::V6.18::ARMCLANG + 1 + + + CT_Board_HS14_M0 + STMicroelectronics + InES.CTBoard14_DFP.4.0.2 + https://ennis.zhaw.ch/pack/ + IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:CT_Board_HS14_M0$Flash\STM32F4xx_2048.FLM)) + 0 + + + + + + + + + + + $$Device:CT_Board_HS14_M0$SVD\STM32F429x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + CT-Lab1-Project + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP-MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + --diag_suppress 6314 + + + + + + + + Source Group 1 + + + utils_ctboard.c + 1 + .\app\utils_ctboard.c + + + task.c + 1 + .\app\task.c + + + + + ::Device + + + ::HAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s + + + + + + + + RTE\Device\CT_Board_HS14_M0\startup_ctboard.s + + + + + + + + RTE\Device\CT_Board_HS14_M0\system_ctboard.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_fmc.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_gpio.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_pwr.c + + + + + + + + RTE\HAL\CT_Board_HS14_M0\hal_rcc.c + + + + + + + + + + diff --git a/CT-Lab1-Project/EventRecorderStub.scvd b/CT-Lab1-Project/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/CT-Lab1-Project/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/CT-Lab1-Project/Listings/CT-Lab1-Project.map b/CT-Lab1-Project/Listings/CT-Lab1-Project.map new file mode 100644 index 0000000..344c63d --- /dev/null +++ b/CT-Lab1-Project/Listings/CT-Lab1-Project.map @@ -0,0 +1,627 @@ +Component: Arm Compiler for Embedded 6.18 Tool: armlink [5e4cc100] + +============================================================================== + +Section Cross References + + utils_ctboard.o(.ARM.exidx.text.read_byte) refers to utils_ctboard.o(.text.read_byte) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.read_halfword) refers to utils_ctboard.o(.text.read_halfword) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.read_word) refers to utils_ctboard.o(.text.read_word) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.read_doubleword) refers to utils_ctboard.o(.text.read_doubleword) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.write_byte) refers to utils_ctboard.o(.text.write_byte) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.write_halfword) refers to utils_ctboard.o(.text.write_halfword) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.write_word) refers to utils_ctboard.o(.text.write_word) for [Anonymous Symbol] + utils_ctboard.o(.ARM.exidx.text.write_doubleword) refers to utils_ctboard.o(.text.write_doubleword) for [Anonymous Symbol] + task.o(.text.main) refers to utils_ctboard.o(.text.read_word) for read_word + task.o(.text.main) refers to utils_ctboard.o(.text.write_word) for write_word + task.o(.text.main) refers to utils_ctboard.o(.text.read_byte) for read_byte + task.o(.text.main) refers to task.o(.text.getData7Segment) for getData7Segment + task.o(.text.main) refers to utils_ctboard.o(.text.write_byte) for write_byte + task.o(.ARM.exidx.text.main) refers to task.o(.text.main) for [Anonymous Symbol] + task.o(.ARM.exidx.text.getData7Segment) refers to task.o(.text.getData7Segment) for [Anonymous Symbol] + task.o(.ARM.exidx.text.getData7SegmentTwoDigits) refers to task.o(.text.getData7SegmentTwoDigits) for [Anonymous Symbol] + datainit_ctboard.o(.text) refers (Weak) to startup_ctboard.o(STACK) for Stack_Mem + datainit_ctboard.o(.text) refers to task.o(.text.main) for main + startup_ctboard.o(RESET) refers to startup_ctboard.o(STACK) for __initial_sp + startup_ctboard.o(RESET) refers to startup_ctboard.o(.text) for Reset_Handler + startup_ctboard.o(.text) refers to system_ctboard.o(.text.__system) for __system + startup_ctboard.o(.text) refers to datainit_ctboard.o(.text) for __main + system_ctboard.o(.text.__system) refers to system_ctboard.o(.text.system_enter_run) for system_enter_run + system_ctboard.o(.ARM.exidx.text.__system) refers to system_ctboard.o(.text.__system) for [Anonymous Symbol] + system_ctboard.o(.text.system_enter_run) refers to system_ctboard.o(.text.init_SystemClock) for init_SystemClock + system_ctboard.o(.text.system_enter_run) refers to system_ctboard.o(.text.init_FPU) for init_FPU + system_ctboard.o(.text.system_enter_run) refers to system_ctboard.o(.text.init_FMC_SRAM) for init_FMC_SRAM + system_ctboard.o(.text.system_enter_run) refers to system_ctboard.o(.text.init_LCD) for init_LCD + system_ctboard.o(.ARM.exidx.text.system_enter_run) refers to system_ctboard.o(.text.system_enter_run) for [Anonymous Symbol] + system_ctboard.o(.text.init_SystemClock) refers to hal_rcc.o(.text.hal_rcc_reset) for hal_rcc_reset + system_ctboard.o(.text.init_SystemClock) refers to hal_rcc.o(.text.hal_rcc_set_osc) for hal_rcc_set_osc + system_ctboard.o(.text.init_SystemClock) refers to hal_rcc.o(.text.hal_rcc_setup_pll) for hal_rcc_setup_pll + system_ctboard.o(.text.init_SystemClock) refers to hal_pwr.o(.text.hal_pwr_set_overdrive) for hal_pwr_set_overdrive + system_ctboard.o(.text.init_SystemClock) refers to hal_rcc.o(.text.hal_rcc_setup_clock) for hal_rcc_setup_clock + system_ctboard.o(.ARM.exidx.text.init_SystemClock) refers to system_ctboard.o(.text.init_SystemClock) for [Anonymous Symbol] + system_ctboard.o(.ARM.exidx.text.init_FPU) refers to system_ctboard.o(.text.init_FPU) for [Anonymous Symbol] + system_ctboard.o(.text.init_FMC_SRAM) refers to hal_gpio.o(.text.hal_gpio_init_alternate) for hal_gpio_init_alternate + system_ctboard.o(.text.init_FMC_SRAM) refers to hal_fmc.o(.text.hal_fmc_init_sram) for hal_fmc_init_sram + system_ctboard.o(.ARM.exidx.text.init_FMC_SRAM) refers to system_ctboard.o(.text.init_FMC_SRAM) for [Anonymous Symbol] + system_ctboard.o(.ARM.exidx.text.init_LCD) refers to system_ctboard.o(.text.init_LCD) for [Anonymous Symbol] + system_ctboard.o(.ARM.exidx.text.system_enter_sleep) refers to system_ctboard.o(.text.system_enter_sleep) for [Anonymous Symbol] + system_ctboard.o(.ARM.exidx.text.system_enter_stop) refers to system_ctboard.o(.text.system_enter_stop) for [Anonymous Symbol] + system_ctboard.o(.ARM.exidx.text.system_enter_standby) refers to system_ctboard.o(.text.system_enter_standby) for [Anonymous Symbol] + hal_fmc.o(.ARM.exidx.text.hal_fmc_reset) refers to hal_fmc.o(.text.hal_fmc_reset) for [Anonymous Symbol] + hal_fmc.o(.ARM.exidx.text.hal_fmc_init_sram) refers to hal_fmc.o(.text.hal_fmc_init_sram) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.hal_gpio_reset) refers to hal_gpio.o(.text.hal_gpio_reset) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_init_input) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.text.hal_gpio_init_input) refers to hal_gpio.o(.text.create_pattern_mask) for create_pattern_mask + hal_gpio.o(.ARM.exidx.text.hal_gpio_init_input) refers to hal_gpio.o(.text.hal_gpio_init_input) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.intercept_overwrite_register) refers to hal_gpio.o(.text.intercept_overwrite_register) for [Anonymous Symbol] + hal_gpio.o(.text.create_pattern_mask) refers to aeabi_sdiv.o(.text) for __aeabi_uidiv + hal_gpio.o(.ARM.exidx.text.create_pattern_mask) refers to hal_gpio.o(.text.create_pattern_mask) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_init_analog) refers to hal_gpio.o(.text.hal_gpio_init_input) for hal_gpio_init_input + hal_gpio.o(.text.hal_gpio_init_analog) refers to hal_gpio.o(.text.create_pattern_mask) for create_pattern_mask + hal_gpio.o(.ARM.exidx.text.hal_gpio_init_analog) refers to hal_gpio.o(.text.hal_gpio_init_analog) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_init_output) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.text.hal_gpio_init_output) refers to hal_gpio.o(.text.create_pattern_mask) for create_pattern_mask + hal_gpio.o(.ARM.exidx.text.hal_gpio_init_output) refers to hal_gpio.o(.text.hal_gpio_init_output) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_init_alternate) refers to hal_gpio.o(.text.hal_gpio_init_output) for hal_gpio_init_output + hal_gpio.o(.text.hal_gpio_init_alternate) refers to hal_gpio.o(.text.create_pattern_mask) for create_pattern_mask + hal_gpio.o(.ARM.exidx.text.hal_gpio_init_alternate) refers to hal_gpio.o(.text.hal_gpio_init_alternate) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.hal_gpio_input_read) refers to hal_gpio.o(.text.hal_gpio_input_read) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.hal_gpio_output_read) refers to hal_gpio.o(.text.hal_gpio_output_read) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_output_write) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.ARM.exidx.text.hal_gpio_output_write) refers to hal_gpio.o(.text.hal_gpio_output_write) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_bit_set) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_set) refers to hal_gpio.o(.text.hal_gpio_bit_set) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_bit_reset) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_reset) refers to hal_gpio.o(.text.hal_gpio_bit_reset) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_bit_toggle) refers to hal_gpio.o(.text.intercept_overwrite_register) for intercept_overwrite_register + hal_gpio.o(.text.hal_gpio_bit_toggle) refers to hal_gpio.o(.text.hal_gpio_output_read) for hal_gpio_output_read + hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_toggle) refers to hal_gpio.o(.text.hal_gpio_bit_toggle) for [Anonymous Symbol] + hal_gpio.o(.text.hal_gpio_irq_set) refers to hal_gpio.o(.text.get_syscfg_mask) for get_syscfg_mask + hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_set) refers to hal_gpio.o(.text.hal_gpio_irq_set) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.get_syscfg_mask) refers to hal_gpio.o(.text.get_syscfg_mask) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_status) refers to hal_gpio.o(.text.hal_gpio_irq_status) for [Anonymous Symbol] + hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_clear) refers to hal_gpio.o(.text.hal_gpio_irq_clear) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_reset) refers to hal_pwr.o(.text.hal_pwr_reset) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_backup_domain) refers to hal_pwr.o(.text.hal_pwr_set_backup_domain) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_backup_access) refers to hal_pwr.o(.text.hal_pwr_set_backup_access) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_wakeup_pin) refers to hal_pwr.o(.text.hal_pwr_set_wakeup_pin) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_flash_powerdown) refers to hal_pwr.o(.text.hal_pwr_set_flash_powerdown) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_overdrive) refers to hal_pwr.o(.text.hal_pwr_set_overdrive) for [Anonymous Symbol] + hal_pwr.o(.ARM.exidx.text.hal_pwr_set_underdrive) refers to hal_pwr.o(.text.hal_pwr_set_underdrive) for [Anonymous Symbol] + hal_rcc.o(.ARM.exidx.text.hal_rcc_reset) refers to hal_rcc.o(.text.hal_rcc_reset) for [Anonymous Symbol] + hal_rcc.o(.ARM.exidx.text.hal_rcc_set_peripheral) refers to hal_rcc.o(.text.hal_rcc_set_peripheral) for [Anonymous Symbol] + hal_rcc.o(.ARM.exidx.text.hal_rcc_set_osc) refers to hal_rcc.o(.text.hal_rcc_set_osc) for [Anonymous Symbol] + hal_rcc.o(.ARM.exidx.text.hal_rcc_setup_pll) refers to hal_rcc.o(.text.hal_rcc_setup_pll) for [Anonymous Symbol] + hal_rcc.o(.ARM.exidx.text.hal_rcc_setup_clock) refers to hal_rcc.o(.text.hal_rcc_setup_clock) for [Anonymous Symbol] + aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing utils_ctboard.o(.text), (0 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.read_byte), (8 bytes). + Removing utils_ctboard.o(.text.read_halfword), (16 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.read_halfword), (8 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.read_word), (8 bytes). + Removing utils_ctboard.o(.text.read_doubleword), (18 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.read_doubleword), (8 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.write_byte), (8 bytes). + Removing utils_ctboard.o(.text.write_halfword), (22 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.write_halfword), (8 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.write_word), (8 bytes). + Removing utils_ctboard.o(.text.write_doubleword), (26 bytes). + Removing utils_ctboard.o(.ARM.exidx.text.write_doubleword), (8 bytes). + Removing task.o(.text), (0 bytes). + Removing task.o(.ARM.exidx.text.main), (8 bytes). + Removing task.o(.ARM.exidx.text.getData7Segment), (8 bytes). + Removing task.o(.text.getData7SegmentTwoDigits), (304 bytes). + Removing task.o(.ARM.exidx.text.getData7SegmentTwoDigits), (8 bytes). + Removing task.o(.ARM.use_no_argv), (4 bytes). + Removing startup_ctboard.o(HEAP), (2048 bytes). + Removing system_ctboard.o(.text), (0 bytes). + Removing system_ctboard.o(.ARM.exidx.text.__system), (8 bytes). + Removing system_ctboard.o(.ARM.exidx.text.system_enter_run), (8 bytes). + Removing system_ctboard.o(.ARM.exidx.text.init_SystemClock), (8 bytes). + Removing system_ctboard.o(.ARM.exidx.text.init_FPU), (8 bytes). + Removing system_ctboard.o(.ARM.exidx.text.init_FMC_SRAM), (8 bytes). + Removing system_ctboard.o(.ARM.exidx.text.init_LCD), (8 bytes). + Removing system_ctboard.o(.text.system_enter_sleep), (10 bytes). + Removing system_ctboard.o(.ARM.exidx.text.system_enter_sleep), (8 bytes). + Removing system_ctboard.o(.text.system_enter_stop), (14 bytes). + Removing system_ctboard.o(.ARM.exidx.text.system_enter_stop), (8 bytes). + Removing system_ctboard.o(.text.system_enter_standby), (2 bytes). + Removing system_ctboard.o(.ARM.exidx.text.system_enter_standby), (8 bytes). + Removing hal_fmc.o(.text), (0 bytes). + Removing hal_fmc.o(.text.hal_fmc_reset), (148 bytes). + Removing hal_fmc.o(.ARM.exidx.text.hal_fmc_reset), (8 bytes). + Removing hal_fmc.o(.ARM.exidx.text.hal_fmc_init_sram), (8 bytes). + Removing hal_gpio.o(.text), (0 bytes). + Removing hal_gpio.o(.text.hal_gpio_reset), (120 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_reset), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_init_input), (126 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_init_input), (8 bytes). + Removing hal_gpio.o(.ARM.exidx.text.intercept_overwrite_register), (8 bytes). + Removing hal_gpio.o(.ARM.exidx.text.create_pattern_mask), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_init_analog), (84 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_init_analog), (8 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_init_output), (8 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_init_alternate), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_input_read), (14 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_input_read), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_output_read), (14 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_output_read), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_output_write), (42 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_output_write), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_bit_set), (54 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_set), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_bit_reset), (54 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_reset), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_bit_toggle), (78 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_bit_toggle), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_irq_set), (888 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_set), (8 bytes). + Removing hal_gpio.o(.text.get_syscfg_mask), (272 bytes). + Removing hal_gpio.o(.ARM.exidx.text.get_syscfg_mask), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_irq_status), (76 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_status), (8 bytes). + Removing hal_gpio.o(.text.hal_gpio_irq_clear), (28 bytes). + Removing hal_gpio.o(.ARM.exidx.text.hal_gpio_irq_clear), (8 bytes). + Removing hal_pwr.o(.text), (0 bytes). + Removing hal_pwr.o(.text.hal_pwr_reset), (24 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_reset), (8 bytes). + Removing hal_pwr.o(.text.hal_pwr_set_backup_domain), (164 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_backup_domain), (8 bytes). + Removing hal_pwr.o(.text.hal_pwr_set_backup_access), (52 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_backup_access), (8 bytes). + Removing hal_pwr.o(.text.hal_pwr_set_wakeup_pin), (52 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_wakeup_pin), (8 bytes). + Removing hal_pwr.o(.text.hal_pwr_set_flash_powerdown), (52 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_flash_powerdown), (8 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_overdrive), (8 bytes). + Removing hal_pwr.o(.text.hal_pwr_set_underdrive), (12 bytes). + Removing hal_pwr.o(.ARM.exidx.text.hal_pwr_set_underdrive), (8 bytes). + Removing hal_rcc.o(.text), (0 bytes). + Removing hal_rcc.o(.ARM.exidx.text.hal_rcc_reset), (8 bytes). + Removing hal_rcc.o(.text.hal_rcc_set_peripheral), (420 bytes). + Removing hal_rcc.o(.ARM.exidx.text.hal_rcc_set_peripheral), (8 bytes). + Removing hal_rcc.o(.ARM.exidx.text.hal_rcc_set_osc), (8 bytes). + Removing hal_rcc.o(.ARM.exidx.text.hal_rcc_setup_pll), (8 bytes). + Removing hal_rcc.o(.ARM.exidx.text.hal_rcc_setup_clock), (8 bytes). + +89 unused section(s) (total 5646 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv_div0.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s 0x00000000 Number 0 datainit_ctboard.o ABSOLUTE + RTE/Device/CT_Board_HS14_M0/startup_ctboard.s 0x00000000 Number 0 startup_ctboard.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + hal_fmc.c 0x00000000 Number 0 hal_fmc.o ABSOLUTE + hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE + hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE + hal_rcc.c 0x00000000 Number 0 hal_rcc.o ABSOLUTE + system_ctboard.c 0x00000000 Number 0 system_ctboard.o ABSOLUTE + task.c 0x00000000 Number 0 task.o ABSOLUTE + utils_ctboard.c 0x00000000 Number 0 utils_ctboard.o ABSOLUTE + RESET 0x08000000 Section 428 startup_ctboard.o(RESET) + .text 0x080001ac Section 124 datainit_ctboard.o(.text) + .text 0x08000228 Section 36 startup_ctboard.o(.text) + .text 0x0800024c Section 364 aeabi_sdiv.o(.text) + [Anonymous Symbol] 0x080003b8 Section 0 system_ctboard.o(.text.__system) + create_pattern_mask 0x080003c1 Thumb Code 156 hal_gpio.o(.text.create_pattern_mask) + [Anonymous Symbol] 0x080003c0 Section 0 hal_gpio.o(.text.create_pattern_mask) + [Anonymous Symbol] 0x0800045c Section 0 task.o(.text.getData7Segment) + [Anonymous Symbol] 0x08000548 Section 0 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_0 0x0800077c Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_1 0x08000780 Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_2 0x08000784 Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_3 0x08000788 Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_4 0x0800078c Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_5 0x08000790 Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + __arm_cp.1_6 0x08000794 Number 4 hal_fmc.o(.text.hal_fmc_init_sram) + [Anonymous Symbol] 0x08000798 Section 0 hal_gpio.o(.text.hal_gpio_init_alternate) + [Anonymous Symbol] 0x0800085a Section 0 hal_gpio.o(.text.hal_gpio_init_output) + [Anonymous Symbol] 0x0800092a Section 0 hal_pwr.o(.text.hal_pwr_set_overdrive) + [Anonymous Symbol] 0x08000938 Section 0 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_1 0x080009cc Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_4 0x080009d0 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_6 0x080009d4 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_7 0x080009d8 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_8 0x080009dc Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_9 0x080009e0 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_10 0x080009e4 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_11 0x080009e8 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_12 0x080009ec Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_13 0x080009f0 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_14 0x080009f4 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_15 0x080009f8 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_16 0x080009fc Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_17 0x08000a00 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_18 0x08000a04 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_19 0x08000a08 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_20 0x08000a0c Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_21 0x08000a10 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_22 0x08000a14 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_23 0x08000a18 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_24 0x08000a1c Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_25 0x08000a20 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_26 0x08000a24 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_27 0x08000a28 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_28 0x08000a2c Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_29 0x08000a30 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_30 0x08000a34 Number 4 hal_rcc.o(.text.hal_rcc_reset) + __arm_cp.0_31 0x08000a38 Number 4 hal_rcc.o(.text.hal_rcc_reset) + [Anonymous Symbol] 0x08000a3c Section 0 hal_rcc.o(.text.hal_rcc_set_osc) + __arm_cp.2_0 0x08000b48 Number 4 hal_rcc.o(.text.hal_rcc_set_osc) + __arm_cp.2_2 0x08000b4c Number 4 hal_rcc.o(.text.hal_rcc_set_osc) + [Anonymous Symbol] 0x08000b50 Section 0 hal_rcc.o(.text.hal_rcc_setup_clock) + __arm_cp.4_0 0x08000bf0 Number 4 hal_rcc.o(.text.hal_rcc_setup_clock) + __arm_cp.4_1 0x08000bf4 Number 4 hal_rcc.o(.text.hal_rcc_setup_clock) + [Anonymous Symbol] 0x08000bf8 Section 0 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_0 0x08000d40 Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_1 0x08000d44 Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_2 0x08000d48 Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_3 0x08000d4c Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_4 0x08000d50 Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + __arm_cp.3_5 0x08000d54 Number 4 hal_rcc.o(.text.hal_rcc_setup_pll) + init_FMC_SRAM 0x08000d59 Thumb Code 340 system_ctboard.o(.text.init_FMC_SRAM) + [Anonymous Symbol] 0x08000d58 Section 0 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_0 0x08000eac Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_1 0x08000eb0 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_2 0x08000eb4 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_3 0x08000eb8 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_4 0x08000ebc Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_5 0x08000ec0 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_6 0x08000ec4 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_7 0x08000ec8 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_8 0x08000ecc Number 4 system_ctboard.o(.text.init_FMC_SRAM) + __arm_cp.4_9 0x08000ed0 Number 4 system_ctboard.o(.text.init_FMC_SRAM) + init_FPU 0x08000ed5 Thumb Code 2 system_ctboard.o(.text.init_FPU) + [Anonymous Symbol] 0x08000ed4 Section 0 system_ctboard.o(.text.init_FPU) + init_LCD 0x08000ed9 Thumb Code 32 system_ctboard.o(.text.init_LCD) + [Anonymous Symbol] 0x08000ed8 Section 0 system_ctboard.o(.text.init_LCD) + __arm_cp.5_0 0x08000ef8 Number 4 system_ctboard.o(.text.init_LCD) + init_SystemClock 0x08000efd Thumb Code 196 system_ctboard.o(.text.init_SystemClock) + [Anonymous Symbol] 0x08000efc Section 0 system_ctboard.o(.text.init_SystemClock) + __arm_cp.2_0 0x08000fc0 Number 4 system_ctboard.o(.text.init_SystemClock) + __arm_cp.2_1 0x08000fc4 Number 4 system_ctboard.o(.text.init_SystemClock) + __arm_cp.2_2 0x08000fc8 Number 4 system_ctboard.o(.text.init_SystemClock) + __arm_cp.2_3 0x08000fcc Number 4 system_ctboard.o(.text.init_SystemClock) + __arm_cp.2_4 0x08000fd0 Number 4 system_ctboard.o(.text.init_SystemClock) + intercept_overwrite_register 0x08000fd5 Thumb Code 48 hal_gpio.o(.text.intercept_overwrite_register) + [Anonymous Symbol] 0x08000fd4 Section 0 hal_gpio.o(.text.intercept_overwrite_register) + __arm_cp.2_0 0x08001004 Number 4 hal_gpio.o(.text.intercept_overwrite_register) + __arm_cp.2_1 0x08001008 Number 4 hal_gpio.o(.text.intercept_overwrite_register) + __arm_cp.2_2 0x0800100c Number 4 hal_gpio.o(.text.intercept_overwrite_register) + [Anonymous Symbol] 0x08001010 Section 0 task.o(.text.main) + __arm_cp.0_0 0x08001048 Number 4 task.o(.text.main) + __arm_cp.0_1 0x0800104c Number 4 task.o(.text.main) + __arm_cp.0_2 0x08001050 Number 4 task.o(.text.main) + __arm_cp.0_3 0x08001054 Number 4 task.o(.text.main) + [Anonymous Symbol] 0x08001058 Section 0 utils_ctboard.o(.text.read_byte) + [Anonymous Symbol] 0x08001068 Section 0 utils_ctboard.o(.text.read_word) + [Anonymous Symbol] 0x08001078 Section 0 system_ctboard.o(.text.system_enter_run) + [Anonymous Symbol] 0x0800108c Section 0 utils_ctboard.o(.text.write_byte) + [Anonymous Symbol] 0x080010a2 Section 0 utils_ctboard.o(.text.write_word) + STACK 0x20000000 Section 8192 startup_ctboard.o(STACK) + __initial_sp 0x20002000 Data 0 startup_ctboard.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + Image$$ER_IROM1$$Limit - Undefined Weak Reference + Image$$RW_IRAM1$$Base - Undefined Weak Reference + Image$$RW_IRAM1$$ZI$$Base - Undefined Weak Reference + Image$$RW_IRAM1$$ZI$$Limit - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + __Vectors_Size 0x000001ac Number 0 startup_ctboard.o ABSOLUTE + Stack_Size 0x00002000 Number 0 startup_ctboard.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_ctboard.o(RESET) + __Vectors_End 0x080001ac Data 0 startup_ctboard.o(RESET) + __main 0x080001ad Thumb Code 74 datainit_ctboard.o(.text) + Reset_Handler 0x08000229 Thumb Code 8 startup_ctboard.o(.text) + NMI_Handler 0x08000231 Thumb Code 2 startup_ctboard.o(.text) + HardFault_Handler 0x08000233 Thumb Code 2 startup_ctboard.o(.text) + MemManage_Handler 0x08000235 Thumb Code 2 startup_ctboard.o(.text) + BusFault_Handler 0x08000237 Thumb Code 2 startup_ctboard.o(.text) + UsageFault_Handler 0x08000239 Thumb Code 2 startup_ctboard.o(.text) + SVC_Handler 0x0800023b Thumb Code 2 startup_ctboard.o(.text) + DebugMon_Handler 0x0800023d Thumb Code 2 startup_ctboard.o(.text) + PendSV_Handler 0x0800023f Thumb Code 2 startup_ctboard.o(.text) + SysTick_Handler 0x08000241 Thumb Code 2 startup_ctboard.o(.text) + ADC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN1_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN1_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN1_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN1_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN2_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN2_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN2_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CAN2_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + CRYP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DCMI_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA1_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2D_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + DMA2_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + ETH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + ETH_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI15_10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + EXTI9_5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + FLASH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + FMC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + FPU_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + HASH_RNG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C1_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C1_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C2_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C2_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C3_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + I2C3_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + LTDC_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + LTDC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_FS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_FS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_HS_EP1_IN_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_HS_EP1_OUT_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_HS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + OTG_HS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + PVD_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + RCC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + RTC_Alarm_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + RTC_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SAI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SDIO_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + SPI6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TAMP_STAMP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM1_BRK_TIM9_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM1_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM1_TRG_COM_TIM11_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM1_UP_TIM10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM6_DAC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM8_BRK_TIM12_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM8_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM8_TRG_COM_TIM14_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + TIM8_UP_TIM13_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + UART4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + UART5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + UART7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + UART8_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + USART1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + USART2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + USART3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + USART6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + WWDG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text) + __aeabi_uidiv 0x0800024d Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_uidivmod 0x0800024d Thumb Code 20 aeabi_sdiv.o(.text) + __aeabi_idiv 0x08000261 Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_idivmod 0x08000261 Thumb Code 338 aeabi_sdiv.o(.text) + __system 0x080003b9 Thumb Code 8 system_ctboard.o(.text.__system) + getData7Segment 0x0800045d Thumb Code 236 task.o(.text.getData7Segment) + hal_fmc_init_sram 0x08000549 Thumb Code 564 hal_fmc.o(.text.hal_fmc_init_sram) + hal_gpio_init_alternate 0x08000799 Thumb Code 194 hal_gpio.o(.text.hal_gpio_init_alternate) + hal_gpio_init_output 0x0800085b Thumb Code 208 hal_gpio.o(.text.hal_gpio_init_output) + hal_pwr_set_overdrive 0x0800092b Thumb Code 12 hal_pwr.o(.text.hal_pwr_set_overdrive) + hal_rcc_reset 0x08000939 Thumb Code 148 hal_rcc.o(.text.hal_rcc_reset) + hal_rcc_set_osc 0x08000a3d Thumb Code 268 hal_rcc.o(.text.hal_rcc_set_osc) + hal_rcc_setup_clock 0x08000b51 Thumb Code 160 hal_rcc.o(.text.hal_rcc_setup_clock) + hal_rcc_setup_pll 0x08000bf9 Thumb Code 328 hal_rcc.o(.text.hal_rcc_setup_pll) + main 0x08001011 Thumb Code 56 task.o(.text.main) + read_byte 0x08001059 Thumb Code 16 utils_ctboard.o(.text.read_byte) + read_word 0x08001069 Thumb Code 16 utils_ctboard.o(.text.read_word) + system_enter_run 0x08001079 Thumb Code 20 system_ctboard.o(.text.system_enter_run) + write_byte 0x0800108d Thumb Code 22 utils_ctboard.o(.text.write_byte) + write_word 0x080010a3 Thumb Code 20 utils_ctboard.o(.text.write_word) + Image$$RO$$Limit 0x080010b8 Number 0 anon$$obj.o ABSOLUTE + Image$$RW$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE + Image$$ZI$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE + Stack_Mem 0x20000000 Data 8192 startup_ctboard.o(STACK) + Image$$ZI$$Limit 0x20002000 Number 0 anon$$obj.o ABSOLUTE + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000229 + + Load Region LR_1 (Base: 0x08000000, Size: 0x000010b8, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000010b8, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000001ac Data RO 46 RESET startup_ctboard.o + 0x080001ac 0x080001ac 0x0000007c Code RO 38 .text datainit_ctboard.o + 0x08000228 0x08000228 0x00000024 Code RO 47 * .text startup_ctboard.o + 0x0800024c 0x0800024c 0x0000016c Code RO 168 .text c_p.l(aeabi_sdiv.o) + 0x080003b8 0x080003b8 0x00000008 Code RO 52 .text.__system system_ctboard.o + 0x080003c0 0x080003c0 0x0000009c Code RO 94 .text.create_pattern_mask hal_gpio.o + 0x0800045c 0x0800045c 0x000000ec Code RO 27 .text.getData7Segment task.o + 0x08000548 0x08000548 0x00000250 Code RO 79 .text.hal_fmc_init_sram hal_fmc.o + 0x08000798 0x08000798 0x000000c2 Code RO 100 .text.hal_gpio_init_alternate hal_gpio.o + 0x0800085a 0x0800085a 0x000000d0 Code RO 98 .text.hal_gpio_init_output hal_gpio.o + 0x0800092a 0x0800092a 0x0000000c Code RO 139 .text.hal_pwr_set_overdrive hal_pwr.o + 0x08000936 0x08000936 0x00000002 PAD + 0x08000938 0x08000938 0x00000104 Code RO 150 .text.hal_rcc_reset hal_rcc.o + 0x08000a3c 0x08000a3c 0x00000114 Code RO 154 .text.hal_rcc_set_osc hal_rcc.o + 0x08000b50 0x08000b50 0x000000a8 Code RO 158 .text.hal_rcc_setup_clock hal_rcc.o + 0x08000bf8 0x08000bf8 0x00000160 Code RO 156 .text.hal_rcc_setup_pll hal_rcc.o + 0x08000d58 0x08000d58 0x0000017c Code RO 60 .text.init_FMC_SRAM system_ctboard.o + 0x08000ed4 0x08000ed4 0x00000002 Code RO 58 .text.init_FPU system_ctboard.o + 0x08000ed6 0x08000ed6 0x00000002 PAD + 0x08000ed8 0x08000ed8 0x00000024 Code RO 62 .text.init_LCD system_ctboard.o + 0x08000efc 0x08000efc 0x000000d8 Code RO 56 .text.init_SystemClock system_ctboard.o + 0x08000fd4 0x08000fd4 0x0000003c Code RO 92 .text.intercept_overwrite_register hal_gpio.o + 0x08001010 0x08001010 0x00000048 Code RO 25 .text.main task.o + 0x08001058 0x08001058 0x00000010 Code RO 2 .text.read_byte utils_ctboard.o + 0x08001068 0x08001068 0x00000010 Code RO 6 .text.read_word utils_ctboard.o + 0x08001078 0x08001078 0x00000014 Code RO 54 .text.system_enter_run system_ctboard.o + 0x0800108c 0x0800108c 0x00000016 Code RO 10 .text.write_byte utils_ctboard.o + 0x080010a2 0x080010a2 0x00000014 Code RO 14 .text.write_word utils_ctboard.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x080010b8, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE) + + **** No section assigned to this execution region **** + + + Execution Region ER_ZI (Exec base: 0x20000000, Load base: 0x080010b8, Size: 0x00002000, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 - 0x00002000 Zero RW 44 STACK startup_ctboard.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 124 50 0 0 0 428 datainit_ctboard.o + 592 44 0 0 0 3213 hal_fmc.o + 618 12 0 0 0 8713 hal_gpio.o + 12 0 0 0 0 2018 hal_pwr.o + 1056 152 0 0 0 4848 hal_rcc.o + 36 8 428 0 8192 796 startup_ctboard.o + 662 64 0 0 0 6900 system_ctboard.o + 308 80 0 0 0 1190 task.o + 74 0 0 0 0 1703 utils_ctboard.o + + ---------------------------------------------------------------------- + 3488 410 428 0 8192 29809 Object Totals + 0 0 0 0 0 0 (incl. Generated) + 6 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 364 4 0 0 0 92 aeabi_sdiv.o + + ---------------------------------------------------------------------- + 364 4 0 0 0 92 Library Totals + 0 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 364 4 0 0 0 92 c_p.l + + ---------------------------------------------------------------------- + 364 4 0 0 0 92 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 3852 414 428 0 8192 29677 Grand Totals + 3852 414 428 0 8192 29677 ELF Image Totals + 3852 414 428 0 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 4280 ( 4.18kB) + Total RW Size (RW Data + ZI Data) 8192 ( 8.00kB) + Total ROM Size (Code + RO Data + RW Data) 4280 ( 4.18kB) + +============================================================================== + diff --git a/CT-Lab1-Project/Objects/CT-Lab1-Project.build_log.htm b/CT-Lab1-Project/Objects/CT-Lab1-Project.build_log.htm new file mode 100644 index 0000000..aadf9bf --- /dev/null +++ b/CT-Lab1-Project/Objects/CT-Lab1-Project.build_log.htm @@ -0,0 +1,52 @@ + + +
+
µVision Build Log

+
Tool Versions:

+IDE-Version: µVision V5.37.0.0
+Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Roman Schenk, ZHAW, LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.37.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.18
+Assembler:       Armasm.exe V6.18
+Linker/Locator:  ArmLink.exe V6.18
+Library Manager: ArmAr.exe V6.18
+Hex Converter:   FromElf.exe V6.18
+CPU DLL:         SARMCM3.DLL V5.37.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.6.0
+Target DLL:      UL2CM3.DLL V1.164.7.0
+Dialog DLL:      TARMCM1.DLL V1.14.6.0
+ 
+
Project:

+C:\Users\roman\Documents\CT-Lab1-Project\CT-Lab1-Project.uvprojx
+Project File Date:  09/23/2022
+
+
Output:

+*** Using Compiler 'V6.18', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
+Build target 'Target 1'
+linking...
+.\Objects\CT-Lab1-Project.axf: Error: L6320W: Ignoring --entry command. Cannot find argument 'Reset_Handler'.
+.\Objects\CT-Lab1-Project.axf: Warning: L6320W: Ignoring --first command. Cannot find argument '__Vectors'.
+Not enough information to list image symbols.
+Not enough information to list load addresses in the image map.
+Finished: 2 information, 1 warning and 1 error messages.
+".\Objects\CT-Lab1-Project.axf" - 1 Error(s), 1 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: InES
+                https://ennis.zhaw.ch/pack/InES.CTBoard14_DFP.4.0.2.pack
+                InES.CTBoard14_DFP.4.0.2
+                CT Board 14 (STM32F429ZI) Device Support
+
+
Collection of Component include folders:

+
+
Collection of Component Files used:

+Target not created.
+Build Time Elapsed:  00:00:00
+
+ + diff --git a/CT-Lab1-Project/Objects/CT-Lab1-Project.lnp b/CT-Lab1-Project/Objects/CT-Lab1-Project.lnp new file mode 100644 index 0000000..2dc2575 --- /dev/null +++ b/CT-Lab1-Project/Objects/CT-Lab1-Project.lnp @@ -0,0 +1,6 @@ +--cpu Cortex-M0 +".\objects\utils_ctboard.o" +".\objects\task.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\CT-Lab1-Project.map" -o .\Objects\CT-Lab1-Project.axf \ No newline at end of file diff --git a/CT-Lab1-Project/Objects/CT-Lab1-Project_Target 1.dep b/CT-Lab1-Project/Objects/CT-Lab1-Project_Target 1.dep new file mode 100644 index 0000000..4c8b8e8 --- /dev/null +++ b/CT-Lab1-Project/Objects/CT-Lab1-Project_Target 1.dep @@ -0,0 +1,6 @@ +Dependencies for Project 'CT-Lab1-Project', Target 'Target 1': (DO NOT MODIFY !) +CompilerVersion: 6180000::V6.18::ARMCLANG +F (.\utils_ctboard.c)(0x613F3541)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -D__UVISION_VERSION="537" -o ./objects/utils_ctboard.o -MD) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (utils_ctboard.h)(0x613F3541) +F (.\Task.c)(0x632D5432)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -D__UVISION_VERSION="537" -o ./objects/task.o -MD) diff --git a/CT-Lab1-Project/Objects/task.__i b/CT-Lab1-Project/Objects/task.__i new file mode 100644 index 0000000..97d2c95 --- /dev/null +++ b/CT-Lab1-Project/Objects/task.__i @@ -0,0 +1,5 @@ +-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c +-fno-rtti -funsigned-char -fshort-enums -fshort-wchar +-D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier +-D__UVISION_VERSION="537" +-o ./objects/task.o -MD "Task.c" \ No newline at end of file diff --git a/CT-Lab1-Project/Objects/task.d b/CT-Lab1-Project/Objects/task.d new file mode 100644 index 0000000..55d5f53 --- /dev/null +++ b/CT-Lab1-Project/Objects/task.d @@ -0,0 +1,2 @@ +./objects/task.o: Task.c utils_ctboard.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h diff --git a/CT-Lab1-Project/Objects/task.o b/CT-Lab1-Project/Objects/task.o new file mode 100644 index 0000000..fec35d0 Binary files /dev/null and b/CT-Lab1-Project/Objects/task.o differ diff --git a/CT-Lab1-Project/Objects/utils_ctboard.d b/CT-Lab1-Project/Objects/utils_ctboard.d new file mode 100644 index 0000000..51d989d --- /dev/null +++ b/CT-Lab1-Project/Objects/utils_ctboard.d @@ -0,0 +1,2 @@ +./objects/utils_ctboard.o: utils_ctboard.c \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h utils_ctboard.h diff --git a/CT-Lab1-Project/Objects/utils_ctboard.o b/CT-Lab1-Project/Objects/utils_ctboard.o new file mode 100644 index 0000000..fa7c1e2 Binary files /dev/null and b/CT-Lab1-Project/Objects/utils_ctboard.o differ diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 new file mode 100644 index 0000000..d891d1a --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 @@ -0,0 +1,100 @@ +;* ------------------------------------------------------------------ +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ------------------------------------------------------------------ +;* -- +;* -- Project : CT Board - Cortex M4 +;* -- Description : Data Segment initialisation. +;* -- +;* -- $Id$ +;* ------------------------------------------------------------------ + + +; ------------------------------------------------------------------- +; -- __Main +; ------------------------------------------------------------------- + + AREA |.text|, CODE, READONLY + + IMPORT main + + EXPORT __main + +__main PROC + + ; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args... + IMPORT |Image$$RO$$Limit| [WEAK] + IMPORT |Image$$RW$$Base| [WEAK] + IMPORT |Image$$ZI$$Base| [WEAK] + IMPORT |Image$$ZI$$Limit| [WEAK] + ; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314 + IMPORT |Image$$ER_IROM1$$Limit| [WEAK] + IMPORT |Image$$RW_IRAM1$$Base| [WEAK] + IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK] + IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK] + ; import stack parameter + IMPORT Stack_Size [WEAK] + IMPORT Stack_Mem [WEAK] + + ; switch between command line generated regions and auto scatter file generated regions + LDR R1, =|Image$$RO$$Limit| + CMP R1,#0 + BEQ ScatterFileSymbols +CommandLineSymbols + LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM + LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM + MOV R5, R3 ; start of zero initialized data + LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data + B CondRWLoop +ScatterFileSymbols + LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data + LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM + LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM + MOV R5, R3 ; start of zero initialized data + LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data + B CondRWLoop + + ; init non-zero data +LoopRWCopy LDR R4, [R1] + STR R4, [R2] + ADDS R1, R1, #4 + ADDS R2, R2, #4 +CondRWLoop CMP R2, R3 + BNE LoopRWCopy + + ; init zero-initialized data + MOV R2, R5 + MOV R3, R6 + MOVS R4, #0 + B CondZILoop +LoopZICopy STR R4, [R2] + ADDS R2, R2, #4 +CondZILoop CMP R2, R3 + BNE LoopZICopy + + ; fingerprint stack section + LDR R0, =Stack_Mem + LDR R1, =Stack_Size + LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!) +LoopStack STR R2, [R0] + ADDS R0, R0, #4 + SUBS R1, #4 + BNE LoopStack + + ; go to the user main function + LDR R0, =main + BX R0 + ENDP + + +; ------------------------------------------------------------------- +; -- End of file +; ------------------------------------------------------------------- + + ALIGN + + END diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 new file mode 100644 index 0000000..fd8a0f9 --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 @@ -0,0 +1,439 @@ +;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** +;* File Name : startup_stm32f429_439xx.s +;* Author : MCD Application Team +;* Version : V1.3.0 +;* Date : 08-November-2013 +;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock and the external SRAM/SDRAM mounted +;* on STM324x9I-EVAL boards to be used as data memory +;* (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT Stack_Size + EXPORT Stack_Mem + +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000800 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __system + IMPORT __main + ENTRY + + LDR R0, =__system + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 new file mode 100644 index 0000000..58c804c --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 @@ -0,0 +1,290 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Interface of module system_ctboard. + * Description : Basic system configuration. + * * initialize system clock + * * initialize FMC (SRAM & GPIO) + * + * GPIO FMC pin assignment: + * + * PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10 + * PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11 + * PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12 + * PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13 + * PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14 + * PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15 + * PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2 + * PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3 + * PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4 + * PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24 + * PD11 > FMC_A16 | PE10 > FMC_D7 | | + * PD12 > FMC_A17 | PE11 > FMC_D8 | | + * PD13 > FMC_A18 | PE12 > FMC_D9 | | + * PD14 > FMC_D0 | PE13 > FMC_D10 | | + * PD15 > FMC_D1 | PE14 > FMC_D11 | | + * | PE15 > FMC_D12 | | + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* Standard includes */ +#include + + +/* User includes */ +#include "system_ctboard.h" +#include "reg_stm32f4xx.h" +#include "reg_ctboard.h" + + +/* -- Macros (LCD) + * ------------------------------------------------------------------------- */ + +#define LCD_WAIT 0x1fff + + +/* -- Macros (FMC) + * ------------------------------------------------------------------------- */ + +#define FMC_PORTD_PINMASK 0xfffb +#define FMC_PORTE_PINMASK 0xffff +#define FMC_PORTF_PINMASK 0xf03f +#define FMC_PORTG_PINMASK 0x363f + + +/* -- Local function declarations + * ------------------------------------------------------------------------- */ + +static void init_SystemClock(void); +static void init_FPU(void); +static void init_FMC_SRAM(void); +static void init_LCD(void); + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Entry point used in startup. + */ +void __system(void) +{ + system_enter_run(); +} + + +/* + * See header files + */ +void system_enter_run(void) +{ + /* Initialize RCC / system clock */ + init_SystemClock(); + + /* Iitialize FPU */ + init_FPU(); + + /* Initialize SRAM interface */ + init_FMC_SRAM(); + + /* Initialize LCD on CT-Board */ + init_LCD(); +} + + +/* + * See header file + */ +void system_enter_sleep(hal_pwr_lp_entry_t entry) +{ + /** \note Implement this function if needed. */ +} + + +/* + * See header file + */ +void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry) +{ + /** \note Implement this function if needed. */ +} + + +/* + * See header file + */ +void system_enter_standby(void) +{ + /** \note Implement this function if needed. */ +} + + +/* -- Local function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Configures the System clock source, PLL Multiplier and Divider + * factors, AHB/APBx prescalers and Flash settings. + */ +static void init_SystemClock(void) +{ + hal_rcc_pll_init_t pll_init; + hal_rcc_clk_init_t clk_init; + + /* Enable used periphery */ + PWR_ENABLE(); + + /* Reset */ + hal_rcc_reset(); + PWR_RESET(); + + /* Enable HSE oscillator and proceed if ok */ + if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) { + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= 0x00000000; + PWR->CR |= 0x0000c000; + + /* Configure PLL */ + pll_init.source = HAL_RCC_OSC_HSE; + pll_init.m_divider = 4u; + pll_init.n_factor = 168u; + pll_init.p_divider = 2u; + pll_init.q_divider = 7u; + hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init); + + /* Enable PLL */ + hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE); + + /* Enable overdrive to allow system clock >= 168 MHz */ + hal_pwr_set_overdrive(ENABLE); + + /* Configure Flash prefetch, Instruction cache, Data cache + * and wait state */ + FLASH->ACR = 0x00000705; + + /* Setup system clock */ + clk_init.osc = HAL_RCC_OSC_PLL; + clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz + clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz + clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz + hal_rcc_setup_clock(clk_init); + + } else { + /* If HSE fails to start-up, the application will have wrong clock con- + figuration. User can add here some code to deal with this error */ + } +} + + +/** + * \brief Initialize the floating point unit in M4 mode. + */ +static void init_FPU(void) +{ +#ifdef PLATFORM_M4 + /* No documentation about this, even the registers... */ + + /* set CP10 and CP11 Full Access */ + FPU->CPACR |= ((3u << 20u)|(3u << 22u)); +#endif +} + + +/** + * \brief Setup the flexible memory controller. This function configures the SRAM + * interface for accessing the periphery on the CT Board. + */ +static void init_FMC_SRAM(void) +{ +#ifndef NO_FMC + + hal_gpio_output_t gpio_init; + hal_fmc_sram_init_t sram_init; + hal_fmc_sram_timing_t sram_timing; + + /* Enable used peripherals */ + GPIOD_ENABLE(); + GPIOE_ENABLE(); + GPIOF_ENABLE(); + GPIOG_ENABLE(); + FMC_ENABLE(); + + /* Configure the involved GPIO pins to AF12 (FMC) */ + gpio_init.pupd = HAL_GPIO_PUPD_NOPULL; + gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ; + gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP; + + /* GPIOD configuration (pins: 0,1,3-15) */ + gpio_init.pins = FMC_PORTD_PINMASK; + hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOE configuration (pins: 0-15) */ + gpio_init.pins = FMC_PORTE_PINMASK; + hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOF configuration (pins: 0-5,12-15) */ + gpio_init.pins = FMC_PORTF_PINMASK; + hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */ + gpio_init.pins = FMC_PORTG_PINMASK; + hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init); + + + /* Initialize the synchronous PSRAM on bank 1 */ + sram_init.address_mux = DISABLE; + sram_init.type = HAL_FMC_TYPE_PSRAM; + sram_init.width = HAL_FMC_WIDTH_16B; + sram_init.read_burst = ENABLE; + sram_init.write_enable = ENABLE; + sram_init.write_burst = ENABLE; + sram_init.continous_clock = ENABLE; + + sram_timing.bus_turnaround = 1u; + sram_timing.clk_divider = 15u; + sram_timing.data_latency = 2u; + + hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing); + + + /* Initialize the asynchronous SRAM on bank 2 */ + sram_init.address_mux = DISABLE; + sram_init.type = HAL_FMC_TYPE_SRAM; + sram_init.width = HAL_FMC_WIDTH_16B; + sram_init.read_burst = DISABLE; + sram_init.write_enable = DISABLE; + sram_init.write_burst = DISABLE; + sram_init.continous_clock = DISABLE; + + sram_timing.bus_turnaround = 1u; + sram_timing.address_setup = 11u; + sram_timing.address_hold = 5u; + sram_timing.data_setup = 11u; + sram_timing.mode = HAL_FMC_ACCESS_MODE_A; + + hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing); + +#endif +} + + +/** + * \brief Wait for the LCD controller on the CT Board to be initialized. + * \TODO Possibly adjust LCD controller on CPLD to set status bit + * and wait for it in this function. + */ +static void init_LCD(void) +{ +#ifndef NO_FMC + uint32_t wait_for_lcd = LCD_WAIT; + for(; wait_for_lcd > 0; wait_for_lcd--); +#endif +} + diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s new file mode 100644 index 0000000..d891d1a --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s @@ -0,0 +1,100 @@ +;* ------------------------------------------------------------------ +;* -- _____ ______ _____ - +;* -- |_ _| | ____|/ ____| - +;* -- | | _ __ | |__ | (___ Institute of Embedded Systems - +;* -- | | | '_ \| __| \___ \ Zurich University of - +;* -- _| |_| | | | |____ ____) | Applied Sciences - +;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +;* ------------------------------------------------------------------ +;* -- +;* -- Project : CT Board - Cortex M4 +;* -- Description : Data Segment initialisation. +;* -- +;* -- $Id$ +;* ------------------------------------------------------------------ + + +; ------------------------------------------------------------------- +; -- __Main +; ------------------------------------------------------------------- + + AREA |.text|, CODE, READONLY + + IMPORT main + + EXPORT __main + +__main PROC + + ; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args... + IMPORT |Image$$RO$$Limit| [WEAK] + IMPORT |Image$$RW$$Base| [WEAK] + IMPORT |Image$$ZI$$Base| [WEAK] + IMPORT |Image$$ZI$$Limit| [WEAK] + ; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314 + IMPORT |Image$$ER_IROM1$$Limit| [WEAK] + IMPORT |Image$$RW_IRAM1$$Base| [WEAK] + IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK] + IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK] + ; import stack parameter + IMPORT Stack_Size [WEAK] + IMPORT Stack_Mem [WEAK] + + ; switch between command line generated regions and auto scatter file generated regions + LDR R1, =|Image$$RO$$Limit| + CMP R1,#0 + BEQ ScatterFileSymbols +CommandLineSymbols + LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM + LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM + MOV R5, R3 ; start of zero initialized data + LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data + B CondRWLoop +ScatterFileSymbols + LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data + LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM + LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM + MOV R5, R3 ; start of zero initialized data + LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data + B CondRWLoop + + ; init non-zero data +LoopRWCopy LDR R4, [R1] + STR R4, [R2] + ADDS R1, R1, #4 + ADDS R2, R2, #4 +CondRWLoop CMP R2, R3 + BNE LoopRWCopy + + ; init zero-initialized data + MOV R2, R5 + MOV R3, R6 + MOVS R4, #0 + B CondZILoop +LoopZICopy STR R4, [R2] + ADDS R2, R2, #4 +CondZILoop CMP R2, R3 + BNE LoopZICopy + + ; fingerprint stack section + LDR R0, =Stack_Mem + LDR R1, =Stack_Size + LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!) +LoopStack STR R2, [R0] + ADDS R0, R0, #4 + SUBS R1, #4 + BNE LoopStack + + ; go to the user main function + LDR R0, =main + BX R0 + ENDP + + +; ------------------------------------------------------------------- +; -- End of file +; ------------------------------------------------------------------- + + ALIGN + + END diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s new file mode 100644 index 0000000..fd8a0f9 --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s @@ -0,0 +1,439 @@ +;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** +;* File Name : startup_stm32f429_439xx.s +;* Author : MCD Application Team +;* Version : V1.3.0 +;* Date : 08-November-2013 +;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock and the external SRAM/SDRAM mounted +;* on STM324x9I-EVAL boards to be used as data memory +;* (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT Stack_Size + EXPORT Stack_Mem + +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000800 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __system + IMPORT __main + ENTRY + + LDR R0, =__system + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/system_ctboard.c b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/system_ctboard.c new file mode 100644 index 0000000..58c804c --- /dev/null +++ b/CT-Lab1-Project/RTE/Device/CT_Board_HS14_M0/system_ctboard.c @@ -0,0 +1,290 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Interface of module system_ctboard. + * Description : Basic system configuration. + * * initialize system clock + * * initialize FMC (SRAM & GPIO) + * + * GPIO FMC pin assignment: + * + * PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10 + * PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11 + * PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12 + * PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13 + * PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14 + * PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15 + * PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2 + * PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3 + * PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4 + * PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24 + * PD11 > FMC_A16 | PE10 > FMC_D7 | | + * PD12 > FMC_A17 | PE11 > FMC_D8 | | + * PD13 > FMC_A18 | PE12 > FMC_D9 | | + * PD14 > FMC_D0 | PE13 > FMC_D10 | | + * PD15 > FMC_D1 | PE14 > FMC_D11 | | + * | PE15 > FMC_D12 | | + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* Standard includes */ +#include + + +/* User includes */ +#include "system_ctboard.h" +#include "reg_stm32f4xx.h" +#include "reg_ctboard.h" + + +/* -- Macros (LCD) + * ------------------------------------------------------------------------- */ + +#define LCD_WAIT 0x1fff + + +/* -- Macros (FMC) + * ------------------------------------------------------------------------- */ + +#define FMC_PORTD_PINMASK 0xfffb +#define FMC_PORTE_PINMASK 0xffff +#define FMC_PORTF_PINMASK 0xf03f +#define FMC_PORTG_PINMASK 0x363f + + +/* -- Local function declarations + * ------------------------------------------------------------------------- */ + +static void init_SystemClock(void); +static void init_FPU(void); +static void init_FMC_SRAM(void); +static void init_LCD(void); + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Entry point used in startup. + */ +void __system(void) +{ + system_enter_run(); +} + + +/* + * See header files + */ +void system_enter_run(void) +{ + /* Initialize RCC / system clock */ + init_SystemClock(); + + /* Iitialize FPU */ + init_FPU(); + + /* Initialize SRAM interface */ + init_FMC_SRAM(); + + /* Initialize LCD on CT-Board */ + init_LCD(); +} + + +/* + * See header file + */ +void system_enter_sleep(hal_pwr_lp_entry_t entry) +{ + /** \note Implement this function if needed. */ +} + + +/* + * See header file + */ +void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry) +{ + /** \note Implement this function if needed. */ +} + + +/* + * See header file + */ +void system_enter_standby(void) +{ + /** \note Implement this function if needed. */ +} + + +/* -- Local function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Configures the System clock source, PLL Multiplier and Divider + * factors, AHB/APBx prescalers and Flash settings. + */ +static void init_SystemClock(void) +{ + hal_rcc_pll_init_t pll_init; + hal_rcc_clk_init_t clk_init; + + /* Enable used periphery */ + PWR_ENABLE(); + + /* Reset */ + hal_rcc_reset(); + PWR_RESET(); + + /* Enable HSE oscillator and proceed if ok */ + if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) { + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= 0x00000000; + PWR->CR |= 0x0000c000; + + /* Configure PLL */ + pll_init.source = HAL_RCC_OSC_HSE; + pll_init.m_divider = 4u; + pll_init.n_factor = 168u; + pll_init.p_divider = 2u; + pll_init.q_divider = 7u; + hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init); + + /* Enable PLL */ + hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE); + + /* Enable overdrive to allow system clock >= 168 MHz */ + hal_pwr_set_overdrive(ENABLE); + + /* Configure Flash prefetch, Instruction cache, Data cache + * and wait state */ + FLASH->ACR = 0x00000705; + + /* Setup system clock */ + clk_init.osc = HAL_RCC_OSC_PLL; + clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz + clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz + clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz + hal_rcc_setup_clock(clk_init); + + } else { + /* If HSE fails to start-up, the application will have wrong clock con- + figuration. User can add here some code to deal with this error */ + } +} + + +/** + * \brief Initialize the floating point unit in M4 mode. + */ +static void init_FPU(void) +{ +#ifdef PLATFORM_M4 + /* No documentation about this, even the registers... */ + + /* set CP10 and CP11 Full Access */ + FPU->CPACR |= ((3u << 20u)|(3u << 22u)); +#endif +} + + +/** + * \brief Setup the flexible memory controller. This function configures the SRAM + * interface for accessing the periphery on the CT Board. + */ +static void init_FMC_SRAM(void) +{ +#ifndef NO_FMC + + hal_gpio_output_t gpio_init; + hal_fmc_sram_init_t sram_init; + hal_fmc_sram_timing_t sram_timing; + + /* Enable used peripherals */ + GPIOD_ENABLE(); + GPIOE_ENABLE(); + GPIOF_ENABLE(); + GPIOG_ENABLE(); + FMC_ENABLE(); + + /* Configure the involved GPIO pins to AF12 (FMC) */ + gpio_init.pupd = HAL_GPIO_PUPD_NOPULL; + gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ; + gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP; + + /* GPIOD configuration (pins: 0,1,3-15) */ + gpio_init.pins = FMC_PORTD_PINMASK; + hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOE configuration (pins: 0-15) */ + gpio_init.pins = FMC_PORTE_PINMASK; + hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOF configuration (pins: 0-5,12-15) */ + gpio_init.pins = FMC_PORTF_PINMASK; + hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init); + + /* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */ + gpio_init.pins = FMC_PORTG_PINMASK; + hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init); + + + /* Initialize the synchronous PSRAM on bank 1 */ + sram_init.address_mux = DISABLE; + sram_init.type = HAL_FMC_TYPE_PSRAM; + sram_init.width = HAL_FMC_WIDTH_16B; + sram_init.read_burst = ENABLE; + sram_init.write_enable = ENABLE; + sram_init.write_burst = ENABLE; + sram_init.continous_clock = ENABLE; + + sram_timing.bus_turnaround = 1u; + sram_timing.clk_divider = 15u; + sram_timing.data_latency = 2u; + + hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing); + + + /* Initialize the asynchronous SRAM on bank 2 */ + sram_init.address_mux = DISABLE; + sram_init.type = HAL_FMC_TYPE_SRAM; + sram_init.width = HAL_FMC_WIDTH_16B; + sram_init.read_burst = DISABLE; + sram_init.write_enable = DISABLE; + sram_init.write_burst = DISABLE; + sram_init.continous_clock = DISABLE; + + sram_timing.bus_turnaround = 1u; + sram_timing.address_setup = 11u; + sram_timing.address_hold = 5u; + sram_timing.data_setup = 11u; + sram_timing.mode = HAL_FMC_ACCESS_MODE_A; + + hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing); + +#endif +} + + +/** + * \brief Wait for the LCD controller on the CT Board to be initialized. + * \TODO Possibly adjust LCD controller on CPLD to set status bit + * and wait for it in this function. + */ +static void init_LCD(void) +{ +#ifndef NO_FMC + uint32_t wait_for_lcd = LCD_WAIT; + for(; wait_for_lcd > 0; wait_for_lcd--); +#endif +} + diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 new file mode 100644 index 0000000..e454145 --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_fmc. + * + * The hardware abstraction layer for the memory controller. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_fmc.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define MASK_PERIPH_FMC (0x00000001) +#define MASK_SRAM_ENABLE (0x00000001) + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_fmc_reset(hal_fmc_bank_t bank) +{ + switch (bank) { + default: + case HAL_FMC_SRAM_BANK1: + FMC->SRAM.BCR1 = 0x000030db; + FMC->SRAM.BTR1 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK2: + FMC->SRAM.BCR2 = 0x000030d2; + FMC->SRAM.BTR2 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK3: + FMC->SRAM.BCR3 = 0x000030d2; + FMC->SRAM.BTR3 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK4: + FMC->SRAM.BCR4 = 0x000030d2; + FMC->SRAM.BTR4 = 0x0fffffff; + break; + } +} + + +/* + * See header file + */ +void hal_fmc_init_sram(hal_fmc_bank_t bank, + hal_fmc_sram_init_t init, + hal_fmc_sram_timing_t timing) +{ + uint32_t reg_cr = 0, reg_tr = 0; + + /* Input check */ + timing.address_setup &= 0xf; + timing.address_hold &= 0xf; + if (timing.address_hold < 1u) timing.address_hold = 1u; + timing.data_setup &= 0xff; + if (timing.data_setup < 1u) timing.data_setup = 1u; + timing.bus_turnaround &= 0xf; + + /* Input check clock divider (2..16) */ + if (timing.clk_divider > 16u) timing.clk_divider = 16u; + if (timing.clk_divider < 2u) timing.clk_divider = 2u; + timing.clk_divider -= 1u; // 0b0001 -> clk / 2 + + /* Input check data latency (2..17) */ + if (timing.data_latency > 17u) timing.data_latency = 17u; + if (timing.data_latency < 2u) timing.data_latency = 2u; + timing.data_latency -= 2u; // 0b0000 -> latency = 2 + + /* Process boolean parameter */ + if (init.address_mux == ENABLE) reg_cr |= (1u << 1u); + if (init.read_burst == ENABLE) reg_cr |= (1u << 8u); + if (init.write_enable == ENABLE) reg_cr |= (1u << 12u); + if (init.write_burst == ENABLE) reg_cr |= (1u << 19u); + if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u); + + /* Process non boolean parameter */ + reg_cr |= (init.type << 2u); + reg_cr |= (init.width << 4u); + + /* Process timing for async. SRAM */ + if (init.type == HAL_FMC_TYPE_SRAM) { + reg_tr |= (timing.address_setup << 0u); + reg_tr |= (timing.address_hold << 4u); + reg_tr |= (timing.data_setup << 8u); + reg_tr |= (timing.mode << 28u); + } + /* Process timing for sync. PSRAM */ + else if (init.type == HAL_FMC_TYPE_PSRAM) { + reg_tr |= (timing.clk_divider << 20u); + reg_tr |= (timing.data_latency << 24u); + } + /* Process bus turnaround time */ + reg_tr |= (timing.bus_turnaround << 16u); + + /* Write register */ + switch (bank) { + default: + case HAL_FMC_SRAM_BANK1: + FMC->SRAM.BCR1 = reg_cr; + FMC->SRAM.BTR1 = reg_tr; + FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK2: + FMC->SRAM.BCR2 = reg_cr; + FMC->SRAM.BTR2 = reg_tr; + FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK3: + FMC->SRAM.BCR3 = reg_cr; + FMC->SRAM.BTR3 = reg_tr; + FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK4: + FMC->SRAM.BCR4 = reg_cr; + FMC->SRAM.BTR4 = reg_tr; + FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE; + break; + } +} + diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 new file mode 100644 index 0000000..59e0e4c --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 @@ -0,0 +1,412 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_gpio. + * + * The hardware abstraction layer for the GPIO periphery. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_gpio.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define NVIC_OFFSET_1_4 ( 6u) +#define NVIC_OFFSET_5_9 (23u) +#define NVIC_OFFSET_10_15 ( 8u) + + +/* -- Local function declarations + * ------------------------------------------------------------------------- */ + +static uint32_t create_pattern_mask(uint16_t pins, + uint8_t pattern, + uint8_t pattern_bit_width); +static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins); +static uint8_t get_syscfg_mask(reg_gpio_t *port); + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_gpio_reset(reg_gpio_t *port) +{ + if(port == GPIOA) { + /* Reset GPIOA specific values */ + port->MODER = 0xa8000000; + port->OSPEEDR = 0x00000000; + port->PUPDR = 0x64000000; + } + else if (port == GPIOB) { + /* Reset GPIOB specific values */ + port->MODER = 0x00000280; + port->OSPEEDR = 0x000000c0; + port->PUPDR = 0x00000100; + } else { + /* Reset other GPIO */ + port->MODER = 0x00000000; + port->OSPEEDR = 0x00000000; + port->PUPDR = 0x00000000; + } + + port->OTYPER = 0x00000000; + port->AFRL = 0x00000000; + port->AFRH = 0x00000000; + port->ODR = 0x00000000; +} + +/* + * See header file + */ +void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init) +{ + /* prevent overwrite false reg entry */ + init.pins = intercept_overwrite_register(port, init.pins); + + /* process mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u); + + /* process pull up/down resitors */ + port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u); +} + + +/* + * See header file + */ +void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init) +{ + /* treat like input */ + hal_gpio_init_input(port, init); + + /* change mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u); +} + + +/* + * See header file + */ +void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init) +{ + /* prevent overwrite false reg entry */ + init.pins = intercept_overwrite_register(port, init.pins); + + /* process mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u); + + /* process pull up/down resitors */ + port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u); + + /* process port speed */ + port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u); + + /* process output typ */ + port->OTYPER &= ~init.pins; + if(init.out_type == HAL_GPIO_OUT_TYPE_OD){ + port->OTYPER |= init.pins; + } +} + + +/* + * See header file + */ +void hal_gpio_init_alternate(reg_gpio_t *port, + hal_gpio_af_t af_mode, + hal_gpio_output_t init) +{ + /* treat like output */ + hal_gpio_init_output(port, init); + + /* change mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u); + + /* process af type */ + port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u); + port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u); + port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u); + port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u); +} + + +/* + * See header file + */ +uint16_t hal_gpio_input_read(reg_gpio_t *port) +{ + return (uint16_t) port->IDR; +} + + +/* + * See header file + */ +uint16_t hal_gpio_output_read(reg_gpio_t *port) +{ + return (uint16_t) port->ODR; +} + + +/* + * See header file + */ +void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value) +{ + /* prevent overwrite false reg entry */ + port_value = intercept_overwrite_register(port, port_value); + port->ODR = port_value; +} + + +/* + * See header file + */ +void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins) +{ + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + port->BSRR = pins; + } +} + + +/* + * See header file + */ +void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins) +{ + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + port->BSRR = (pins << 16); + } +} + + +/* + * See header file + */ +void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins) +{ + uint16_t pattern; + + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + /* get actual value and invert */ + pattern = hal_gpio_output_read(port); + pattern = ~pattern; + + /* mask pins */ + pattern &= pins; + + port->ODR = pattern; + } +} + + +/* + * See header file + */ +void hal_gpio_irq_set(reg_gpio_t *port, + uint16_t pins, + hal_gpio_trg_t edge, + hal_bool_t status) +{ + uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line; + uint32_t exticr_mask; + + for (exti_line = 0u; exti_line < 16u; exti_line++) { + if (pins & (0x1 << exti_line)) { + syscfg_bank = exti_line / 4u; + syscfg_shift = exti_line % 4u; + nvic_bank = (exti_line < 10u) ? 0u : 1u; + + if (status == ENABLE) { + /* Trigger (rising/falling/both) */ + if (edge & HAL_GPIO_TRG_POS) { + EXTI->RTSR |= (0x1 << exti_line); + } + if (edge & HAL_GPIO_TRG_NEG) { + EXTI->FTSR |= (0x1 << exti_line); + } + /* Set EXTI line to corresponding GPIO port */ + exticr_mask = get_syscfg_mask(port); + if (syscfg_bank == 0u) { + SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 1u) { + SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 2u) { + SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 3u) { + SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift); + } + + /* Unmask interrupt */ + EXTI->IMR |= (0x1 << exti_line); + if (nvic_bank == 0u) { + NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 1u) { + NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 2u) { + NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } + + } else { + /* Mask interrupt */ + EXTI->IMR &= ~(0x1 << exti_line); + if (nvic_bank == 0u) { + NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 1u) { + NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 2u) { + NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } + } + } + } + +} + + +/* + * See header file + */ +hal_bool_t hal_gpio_irq_status(uint16_t pin) +{ + hal_bool_t status = DISABLED; + + if ((EXTI->IMR && pin) && + (EXTI->PR && pin)) { + status = ENABLED; + } + + return status; +} + + +/* + * See header file + */ +void hal_gpio_irq_clear(uint16_t pin) +{ + EXTI->PR |= pin; +} + + +/* -- Local function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Creates a pattern based on specified pins. + * + * example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide) + * ==> pattern = 0x0000'0288 + * + * 0b0..0'0001'1010 / 0b10 (2 bit wide) + * ^ ^ ^ + * ==> 0b0..0'00010'1000'1000 + * ^^ ^^ ^^ + * + * pattern_bit_width must be 2 or 4 + */ +static uint32_t create_pattern_mask(uint16_t pins, + uint8_t pattern, + uint8_t pattern_bit_width) +{ + const uint8_t mask_bit_width = 32u; + const uint16_t pin1_mask = 1u; + + uint8_t pos, end; + uint32_t mask = 0u; + + if (pattern_bit_width == 2u || pattern_bit_width == 4u) { + /* create pattern mask */ + end = mask_bit_width / pattern_bit_width; + for (pos = 0; pos < end; pos++) { + if (pins & pin1_mask) { + mask |= pattern << (pos * pattern_bit_width); + } + pins >>= 1; + } + } else { + /* exit if pattern_bit_width not as needed */ + mask = 0u; + } + + return mask; +} + + +/** + * \brief This function ensures that these sensitive pins are not reconfigured. + * + * On GPIOA and GPIOB only pins 11 down to 0 are available to the user. + * Pins 15 down to 12 are used for system functions of the discovery board, + * e.g. connection of the debugger. + * These pins must not be reconfigured. Otherwise the debugger cannot be used any more. + */ +static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){ + if (port == GPIOA || port == GPIOB){ + pins &= 0x0FFF; + } + return pins; +} + + +/** + * \brief Returns mask for configuration of SYSCFG_EXTICR register. + * \param port : Port of which the mask should be generated. + * \return Mask for specified port. + */ +static uint8_t get_syscfg_mask(reg_gpio_t *port) +{ + return ((port == GPIOA) ? 0u : + (port == GPIOB) ? 1u : + (port == GPIOC) ? 2u : + (port == GPIOD) ? 3u : + (port == GPIOE) ? 4u : + (port == GPIOF) ? 5u : + (port == GPIOG) ? 6u : + (port == GPIOH) ? 7u : + (port == GPIOI) ? 8u : + (port == GPIOJ) ? 9u : 10u); +} diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 new file mode 100644 index 0000000..a244dd6 --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_pwr. + * + * The hardware abstraction layer for the power control unit. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_pwr.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define TIME_OUT 0x1000 +#define MASK_PERIPH_PWR (1u << 28u) + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_pwr_reset(void) +{ + /* Reset peripheral */ + PWR->CR = 0x0000c000; + PWR->CSR = 0x00000000; +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status) +{ + uint16_t count = 0; + uint32_t reg = 0; + + if (status == DISABLE) { + /* Disable backup domain / regulator */ + PWR->CSR &= ~(1u << 9u); + return DISABLED; + } + + /* Enable backup domain / regulator */ + PWR->CSR |= (1u << 9u); + + /* Wait till regulator is ready and if time out is reached exit */ + reg = PWR->CSR & (1u << 3u); + while ((reg == 0) && (count != TIME_OUT)) { + reg = PWR->CSR & (1u << 3u); + count++; + } + + /* Return */ + if (reg != 0) { + return ENABLED; + } + return DISABLED; +} + + +/* + * See header file + */ +void hal_pwr_set_backup_access(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CR &= ~(1u << 8u); + } else { + PWR->CR |= (1u << 8u); + } +} + + +/* + * See header file + */ +void hal_pwr_set_wakeup_pin(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CSR &= ~(1u << 8u); + } else { + PWR->CSR |= (1u << 8u); + } +} + + +/* + * See header file + */ +void hal_pwr_set_flash_powerdown(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CR &= ~(1u << 9u); + } else { + PWR->CR |= (1u << 9u); + } +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_overdrive(hal_bool_t status) +{ + /* Is this realy nedded ? + Extend clock to 180 MHz if HSI/HSE is used, but pll ? */ + return DISABLED; +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_underdrive(hal_bool_t status) +{ + /* Is this realy nedded ? */ + return DISABLED; +} diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 new file mode 100644 index 0000000..fdd4d3a --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 @@ -0,0 +1,347 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_rcc. + * + * The hardware abstraction layer for the reset and clock control unit. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_rcc.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define TIME_OUT 0x5000 + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_rcc_reset(void) +{ + /* Set RCC->CR to default values */ + RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running + RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S, + // PLLSAI bits (STM32F42xx/43xx) + RCC->CR &= 0xfffbffff; // Reset HSEBYP bit + + /* Reset RCC->CFGR to default values */ + RCC->CFGR = 0u; + + /* Reset RCC->PLLxCFGR to default values */ + RCC->PLLCFGR = 0x24003010; + RCC->PLLI2SCFGR = 0x20003000; + RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx) + + /* Disable all interrupts */ + RCC->CIR = 0u; + + /* Disable all peripherals */ + RCC->AHB1RSTR = 0u; + RCC->AHB2RSTR = 0u; + RCC->AHB3RSTR = 0u; + RCC->APB1RSTR = 0u; + RCC->APB2RSTR = 0u; + RCC->AHB1ENR = 0x00100000; + RCC->AHB2ENR = 0u; + RCC->AHB3ENR = 0u; + RCC->APB1ENR = 0u; + RCC->APB2ENR = 0u; + RCC->AHB1LPENR = 0x7e6791ff; + RCC->AHB2LPENR = 0x000000f1; + RCC->AHB3LPENR = 0x00000001; + RCC->APB1LPENR = 0x36fec9ff; + RCC->APB2LPENR = 0x00075f33; + + /* Reset forgotten registers */ + RCC->BDCR = 0u; + RCC->CSR = 0x0e000000; + RCC->SSCGR = 0u; + RCC->DCKCFGR = 0u; +} + + +/* + * See header file + */ +void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status) +{ + volatile uint32_t *reg; + uint32_t bit_pos; + + /* Select correct enable register */ + switch (peripheral) { + /* AHB1 */ + case PER_GPIOA: + bit_pos = 0u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOB: + bit_pos = 1u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOC: + bit_pos = 2u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOD: + bit_pos = 3u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOE: + bit_pos = 4u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOF: + bit_pos = 5u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOG: + bit_pos = 6u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOH: + bit_pos = 7u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOI: + bit_pos = 8u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOJ: + bit_pos = 9u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOK: + bit_pos = 10u; + reg = &RCC->AHB1ENR; + break; + case PER_DMA1: + bit_pos = 21u; + reg = &RCC->AHB1ENR; + break; + case PER_DMA2: + bit_pos = 22u; + reg = &RCC->AHB1ENR; + break; + + /* AHB3 */ + case PER_FMC: + bit_pos = 0u; + reg = &RCC->AHB3ENR; + break; + + /* APB1 */ + case PER_DAC: + bit_pos = 29u; + reg = &RCC->APB1ENR; + break; + case PER_PWR: + bit_pos = 28u; + reg = &RCC->APB1ENR; + break; + case PER_TIM2: + bit_pos = 0u; + reg = &RCC->APB1ENR; + break; + case PER_TIM3: + bit_pos = 1u; + reg = &RCC->APB1ENR; + break; + case PER_TIM4: + bit_pos = 2u; + reg = &RCC->APB1ENR; + break; + case PER_TIM5: + bit_pos = 3u; + reg = &RCC->APB1ENR; + break; + + + /* APB2 */ + case PER_ADC1: + bit_pos = 8u; + reg = &RCC->APB2ENR; + break; + case PER_ADC2: + bit_pos = 9u; + reg = &RCC->APB2ENR; + break; + case PER_ADC3: + bit_pos = 10u; + reg = &RCC->APB2ENR; + break; + + default: + return; + } + + if (status == DISABLE) { + *reg &= ~(1u << bit_pos); + } else { + *reg |= (1u << bit_pos); + } +} + + +/* + * See header file + */ +hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status) +{ + uint32_t reg = 0; + uint32_t count = 0; + + /* Disable source */ + if (status == DISABLE) { + RCC->CR &= ~(1u << source); + return DISABLED; + } + + /* If pll, check if source is ok */ + if (source == HAL_RCC_OSC_PLL || + source == HAL_RCC_OSC_PLLI2S || + source == HAL_RCC_OSC_PLLSAI) + { + reg = RCC->CR; + /* HSE */ + if (RCC->PLLCFGR & ~(1u << 22u)) { + reg &= (1u << (HAL_RCC_OSC_HSE + 1u)); + } + /* HSI */ + else { + reg &= (1u << (HAL_RCC_OSC_HSI + 1u)); + } + /* Return if source is not ok */ + if (!reg) { + return DISABLED; + } + } + + /* Enable source */ + RCC->CR |= (1u << source); + + /* Wait till source is ready and if time out is reached exit */ + reg = RCC->CR & (1u << (source + 1u)); + while ((reg == 0) && (count != TIME_OUT)) { + reg = RCC->CR & (1u << (source + 1u)); + count++; + } + + /* Return */ + if (reg != 0) { + return ENABLED; + } + return DISABLED; +} + + +/* + * See header file + */ +void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init) +{ + /* Input check */ + if (init.m_divider < 2u) init.m_divider = 2u; + + if (init.n_factor < 2u) init.n_factor = 2u; + if (init.n_factor > 432u) init.n_factor = 432u; + + if (init.p_divider > 8u) init.p_divider = 8u; + + if (init.q_divider < 2u) init.q_divider = 2u; + + init.r_divider &= 0x07; + + /* Set source or return if invalid */ + if (init.source == HAL_RCC_OSC_HSI) { + RCC->PLLCFGR &= ~(1u << 22u); + } else if (init.source == HAL_RCC_OSC_HSE) { + RCC->PLLCFGR |= (1u << 22u); + } else { + return; + } + + /* Set pll preescaler */ + RCC->PLLCFGR &= ~(0x3f); + RCC->PLLCFGR |= init.m_divider; + + /* Configure pll */ + switch (pll) { + case HAL_RCC_OSC_PLL: + RCC->PLLCFGR &= ~0x0f037fc0; + RCC->PLLCFGR |= (init.n_factor << 6u); + RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u); + RCC->PLLCFGR |= (init.q_divider << 24u); + break; + + case HAL_RCC_OSC_PLLI2S: + RCC->PLLI2SCFGR &= ~0x7f007fc0; + RCC->PLLI2SCFGR |= (init.n_factor << 6u); + RCC->PLLI2SCFGR |= (init.q_divider << 24u); + RCC->PLLI2SCFGR |= (init.r_divider << 28u); + break; + +/* case HAL_RCC_OSC_PLLSAI: + RCC->PLLSAICFGR &= ~0x7f007fc0; + RCC->PLLSAICFGR |= (init.n_factor << 6u); + RCC->PLLSAICFGR |= (init.q_divider << 24u); + RCC->PLLSAICFGR |= (init.r_divider << 28u); + break; +*/ + default: + break; + } +} + + +/* + * See header file + */ +void hal_rcc_setup_clock(hal_rcc_clk_init_t init) +{ + uint32_t reg = 0; + + /* Configure clock divider */ + RCC->CFGR &= ~0x0000fcf0; + RCC->CFGR |= (init.hpre << 4u); + RCC->CFGR |= (init.ppre1 << 10u); + RCC->CFGR |= (init.ppre2 << 13u); + + /* Select system clock source */ + RCC->CFGR &= ~0x00000003; + switch (init.osc) { + default: + case HAL_RCC_OSC_HSI: + reg = 0u; + break; + + case HAL_RCC_OSC_HSE: + reg = 1u; + break; + + case HAL_RCC_OSC_PLL: + reg = 2u; + break; + } + RCC->CFGR |= reg; + +#ifndef TESTING + /* Wait till system clock is selected */ + while ((RCC->CFGR & 0x0000000c) != (reg << 2u)); +#endif +} diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c new file mode 100644 index 0000000..e454145 --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_fmc. + * + * The hardware abstraction layer for the memory controller. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_fmc.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define MASK_PERIPH_FMC (0x00000001) +#define MASK_SRAM_ENABLE (0x00000001) + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_fmc_reset(hal_fmc_bank_t bank) +{ + switch (bank) { + default: + case HAL_FMC_SRAM_BANK1: + FMC->SRAM.BCR1 = 0x000030db; + FMC->SRAM.BTR1 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK2: + FMC->SRAM.BCR2 = 0x000030d2; + FMC->SRAM.BTR2 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK3: + FMC->SRAM.BCR3 = 0x000030d2; + FMC->SRAM.BTR3 = 0x0fffffff; + break; + + case HAL_FMC_SRAM_BANK4: + FMC->SRAM.BCR4 = 0x000030d2; + FMC->SRAM.BTR4 = 0x0fffffff; + break; + } +} + + +/* + * See header file + */ +void hal_fmc_init_sram(hal_fmc_bank_t bank, + hal_fmc_sram_init_t init, + hal_fmc_sram_timing_t timing) +{ + uint32_t reg_cr = 0, reg_tr = 0; + + /* Input check */ + timing.address_setup &= 0xf; + timing.address_hold &= 0xf; + if (timing.address_hold < 1u) timing.address_hold = 1u; + timing.data_setup &= 0xff; + if (timing.data_setup < 1u) timing.data_setup = 1u; + timing.bus_turnaround &= 0xf; + + /* Input check clock divider (2..16) */ + if (timing.clk_divider > 16u) timing.clk_divider = 16u; + if (timing.clk_divider < 2u) timing.clk_divider = 2u; + timing.clk_divider -= 1u; // 0b0001 -> clk / 2 + + /* Input check data latency (2..17) */ + if (timing.data_latency > 17u) timing.data_latency = 17u; + if (timing.data_latency < 2u) timing.data_latency = 2u; + timing.data_latency -= 2u; // 0b0000 -> latency = 2 + + /* Process boolean parameter */ + if (init.address_mux == ENABLE) reg_cr |= (1u << 1u); + if (init.read_burst == ENABLE) reg_cr |= (1u << 8u); + if (init.write_enable == ENABLE) reg_cr |= (1u << 12u); + if (init.write_burst == ENABLE) reg_cr |= (1u << 19u); + if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u); + + /* Process non boolean parameter */ + reg_cr |= (init.type << 2u); + reg_cr |= (init.width << 4u); + + /* Process timing for async. SRAM */ + if (init.type == HAL_FMC_TYPE_SRAM) { + reg_tr |= (timing.address_setup << 0u); + reg_tr |= (timing.address_hold << 4u); + reg_tr |= (timing.data_setup << 8u); + reg_tr |= (timing.mode << 28u); + } + /* Process timing for sync. PSRAM */ + else if (init.type == HAL_FMC_TYPE_PSRAM) { + reg_tr |= (timing.clk_divider << 20u); + reg_tr |= (timing.data_latency << 24u); + } + /* Process bus turnaround time */ + reg_tr |= (timing.bus_turnaround << 16u); + + /* Write register */ + switch (bank) { + default: + case HAL_FMC_SRAM_BANK1: + FMC->SRAM.BCR1 = reg_cr; + FMC->SRAM.BTR1 = reg_tr; + FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK2: + FMC->SRAM.BCR2 = reg_cr; + FMC->SRAM.BTR2 = reg_tr; + FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK3: + FMC->SRAM.BCR3 = reg_cr; + FMC->SRAM.BTR3 = reg_tr; + FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE; + break; + + case HAL_FMC_SRAM_BANK4: + FMC->SRAM.BCR4 = reg_cr; + FMC->SRAM.BTR4 = reg_tr; + FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE; + break; + } +} + diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c new file mode 100644 index 0000000..59e0e4c --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c @@ -0,0 +1,412 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_gpio. + * + * The hardware abstraction layer for the GPIO periphery. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_gpio.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define NVIC_OFFSET_1_4 ( 6u) +#define NVIC_OFFSET_5_9 (23u) +#define NVIC_OFFSET_10_15 ( 8u) + + +/* -- Local function declarations + * ------------------------------------------------------------------------- */ + +static uint32_t create_pattern_mask(uint16_t pins, + uint8_t pattern, + uint8_t pattern_bit_width); +static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins); +static uint8_t get_syscfg_mask(reg_gpio_t *port); + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_gpio_reset(reg_gpio_t *port) +{ + if(port == GPIOA) { + /* Reset GPIOA specific values */ + port->MODER = 0xa8000000; + port->OSPEEDR = 0x00000000; + port->PUPDR = 0x64000000; + } + else if (port == GPIOB) { + /* Reset GPIOB specific values */ + port->MODER = 0x00000280; + port->OSPEEDR = 0x000000c0; + port->PUPDR = 0x00000100; + } else { + /* Reset other GPIO */ + port->MODER = 0x00000000; + port->OSPEEDR = 0x00000000; + port->PUPDR = 0x00000000; + } + + port->OTYPER = 0x00000000; + port->AFRL = 0x00000000; + port->AFRH = 0x00000000; + port->ODR = 0x00000000; +} + +/* + * See header file + */ +void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init) +{ + /* prevent overwrite false reg entry */ + init.pins = intercept_overwrite_register(port, init.pins); + + /* process mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u); + + /* process pull up/down resitors */ + port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u); +} + + +/* + * See header file + */ +void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init) +{ + /* treat like input */ + hal_gpio_init_input(port, init); + + /* change mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u); +} + + +/* + * See header file + */ +void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init) +{ + /* prevent overwrite false reg entry */ + init.pins = intercept_overwrite_register(port, init.pins); + + /* process mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u); + + /* process pull up/down resitors */ + port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u); + + /* process port speed */ + port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u); + + /* process output typ */ + port->OTYPER &= ~init.pins; + if(init.out_type == HAL_GPIO_OUT_TYPE_OD){ + port->OTYPER |= init.pins; + } +} + + +/* + * See header file + */ +void hal_gpio_init_alternate(reg_gpio_t *port, + hal_gpio_af_t af_mode, + hal_gpio_output_t init) +{ + /* treat like output */ + hal_gpio_init_output(port, init); + + /* change mode */ + port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u); + port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u); + + /* process af type */ + port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u); + port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u); + port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u); + port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u); +} + + +/* + * See header file + */ +uint16_t hal_gpio_input_read(reg_gpio_t *port) +{ + return (uint16_t) port->IDR; +} + + +/* + * See header file + */ +uint16_t hal_gpio_output_read(reg_gpio_t *port) +{ + return (uint16_t) port->ODR; +} + + +/* + * See header file + */ +void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value) +{ + /* prevent overwrite false reg entry */ + port_value = intercept_overwrite_register(port, port_value); + port->ODR = port_value; +} + + +/* + * See header file + */ +void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins) +{ + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + port->BSRR = pins; + } +} + + +/* + * See header file + */ +void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins) +{ + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + port->BSRR = (pins << 16); + } +} + + +/* + * See header file + */ +void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins) +{ + uint16_t pattern; + + /* prevent overwrite false reg entry */ + pins = intercept_overwrite_register(port, pins); + + /* exit if no pins to be configured */ + if (pins != 0) { + /* get actual value and invert */ + pattern = hal_gpio_output_read(port); + pattern = ~pattern; + + /* mask pins */ + pattern &= pins; + + port->ODR = pattern; + } +} + + +/* + * See header file + */ +void hal_gpio_irq_set(reg_gpio_t *port, + uint16_t pins, + hal_gpio_trg_t edge, + hal_bool_t status) +{ + uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line; + uint32_t exticr_mask; + + for (exti_line = 0u; exti_line < 16u; exti_line++) { + if (pins & (0x1 << exti_line)) { + syscfg_bank = exti_line / 4u; + syscfg_shift = exti_line % 4u; + nvic_bank = (exti_line < 10u) ? 0u : 1u; + + if (status == ENABLE) { + /* Trigger (rising/falling/both) */ + if (edge & HAL_GPIO_TRG_POS) { + EXTI->RTSR |= (0x1 << exti_line); + } + if (edge & HAL_GPIO_TRG_NEG) { + EXTI->FTSR |= (0x1 << exti_line); + } + /* Set EXTI line to corresponding GPIO port */ + exticr_mask = get_syscfg_mask(port); + if (syscfg_bank == 0u) { + SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 1u) { + SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 2u) { + SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift); + } else if (syscfg_bank == 3u) { + SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift); + SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift); + } + + /* Unmask interrupt */ + EXTI->IMR |= (0x1 << exti_line); + if (nvic_bank == 0u) { + NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 1u) { + NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 2u) { + NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } + + } else { + /* Mask interrupt */ + EXTI->IMR &= ~(0x1 << exti_line); + if (nvic_bank == 0u) { + NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 1u) { + NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } else if (nvic_bank == 2u) { + NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) : + (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15); + } + } + } + } + +} + + +/* + * See header file + */ +hal_bool_t hal_gpio_irq_status(uint16_t pin) +{ + hal_bool_t status = DISABLED; + + if ((EXTI->IMR && pin) && + (EXTI->PR && pin)) { + status = ENABLED; + } + + return status; +} + + +/* + * See header file + */ +void hal_gpio_irq_clear(uint16_t pin) +{ + EXTI->PR |= pin; +} + + +/* -- Local function definitions + * ------------------------------------------------------------------------- */ + +/** + * \brief Creates a pattern based on specified pins. + * + * example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide) + * ==> pattern = 0x0000'0288 + * + * 0b0..0'0001'1010 / 0b10 (2 bit wide) + * ^ ^ ^ + * ==> 0b0..0'00010'1000'1000 + * ^^ ^^ ^^ + * + * pattern_bit_width must be 2 or 4 + */ +static uint32_t create_pattern_mask(uint16_t pins, + uint8_t pattern, + uint8_t pattern_bit_width) +{ + const uint8_t mask_bit_width = 32u; + const uint16_t pin1_mask = 1u; + + uint8_t pos, end; + uint32_t mask = 0u; + + if (pattern_bit_width == 2u || pattern_bit_width == 4u) { + /* create pattern mask */ + end = mask_bit_width / pattern_bit_width; + for (pos = 0; pos < end; pos++) { + if (pins & pin1_mask) { + mask |= pattern << (pos * pattern_bit_width); + } + pins >>= 1; + } + } else { + /* exit if pattern_bit_width not as needed */ + mask = 0u; + } + + return mask; +} + + +/** + * \brief This function ensures that these sensitive pins are not reconfigured. + * + * On GPIOA and GPIOB only pins 11 down to 0 are available to the user. + * Pins 15 down to 12 are used for system functions of the discovery board, + * e.g. connection of the debugger. + * These pins must not be reconfigured. Otherwise the debugger cannot be used any more. + */ +static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){ + if (port == GPIOA || port == GPIOB){ + pins &= 0x0FFF; + } + return pins; +} + + +/** + * \brief Returns mask for configuration of SYSCFG_EXTICR register. + * \param port : Port of which the mask should be generated. + * \return Mask for specified port. + */ +static uint8_t get_syscfg_mask(reg_gpio_t *port) +{ + return ((port == GPIOA) ? 0u : + (port == GPIOB) ? 1u : + (port == GPIOC) ? 2u : + (port == GPIOD) ? 3u : + (port == GPIOE) ? 4u : + (port == GPIOF) ? 5u : + (port == GPIOG) ? 6u : + (port == GPIOH) ? 7u : + (port == GPIOI) ? 8u : + (port == GPIOJ) ? 9u : 10u); +} diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c new file mode 100644 index 0000000..a244dd6 --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_pwr. + * + * The hardware abstraction layer for the power control unit. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_pwr.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define TIME_OUT 0x1000 +#define MASK_PERIPH_PWR (1u << 28u) + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_pwr_reset(void) +{ + /* Reset peripheral */ + PWR->CR = 0x0000c000; + PWR->CSR = 0x00000000; +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status) +{ + uint16_t count = 0; + uint32_t reg = 0; + + if (status == DISABLE) { + /* Disable backup domain / regulator */ + PWR->CSR &= ~(1u << 9u); + return DISABLED; + } + + /* Enable backup domain / regulator */ + PWR->CSR |= (1u << 9u); + + /* Wait till regulator is ready and if time out is reached exit */ + reg = PWR->CSR & (1u << 3u); + while ((reg == 0) && (count != TIME_OUT)) { + reg = PWR->CSR & (1u << 3u); + count++; + } + + /* Return */ + if (reg != 0) { + return ENABLED; + } + return DISABLED; +} + + +/* + * See header file + */ +void hal_pwr_set_backup_access(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CR &= ~(1u << 8u); + } else { + PWR->CR |= (1u << 8u); + } +} + + +/* + * See header file + */ +void hal_pwr_set_wakeup_pin(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CSR &= ~(1u << 8u); + } else { + PWR->CSR |= (1u << 8u); + } +} + + +/* + * See header file + */ +void hal_pwr_set_flash_powerdown(hal_bool_t status) +{ + if (status == DISABLE) { + PWR->CR &= ~(1u << 9u); + } else { + PWR->CR |= (1u << 9u); + } +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_overdrive(hal_bool_t status) +{ + /* Is this realy nedded ? + Extend clock to 180 MHz if HSI/HSE is used, but pll ? */ + return DISABLED; +} + + +/* + * See header file + */ +hal_bool_t hal_pwr_set_underdrive(hal_bool_t status) +{ + /* Is this realy nedded ? */ + return DISABLED; +} diff --git a/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c new file mode 100644 index 0000000..fdd4d3a --- /dev/null +++ b/CT-Lab1-Project/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c @@ -0,0 +1,347 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ------------------------------------------------------------------------- */ +/** + * \brief Implementation of module hal_rcc. + * + * The hardware abstraction layer for the reset and clock control unit. + * + * $Id$ + * ------------------------------------------------------------------------- */ + +/* User includes */ +#include "hal_rcc.h" +#include "reg_stm32f4xx.h" + + +/* -- Macros + * ------------------------------------------------------------------------- */ + +#define TIME_OUT 0x5000 + + +/* -- Public function definitions + * ------------------------------------------------------------------------- */ + +/* + * See header file + */ +void hal_rcc_reset(void) +{ + /* Set RCC->CR to default values */ + RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running + RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S, + // PLLSAI bits (STM32F42xx/43xx) + RCC->CR &= 0xfffbffff; // Reset HSEBYP bit + + /* Reset RCC->CFGR to default values */ + RCC->CFGR = 0u; + + /* Reset RCC->PLLxCFGR to default values */ + RCC->PLLCFGR = 0x24003010; + RCC->PLLI2SCFGR = 0x20003000; + RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx) + + /* Disable all interrupts */ + RCC->CIR = 0u; + + /* Disable all peripherals */ + RCC->AHB1RSTR = 0u; + RCC->AHB2RSTR = 0u; + RCC->AHB3RSTR = 0u; + RCC->APB1RSTR = 0u; + RCC->APB2RSTR = 0u; + RCC->AHB1ENR = 0x00100000; + RCC->AHB2ENR = 0u; + RCC->AHB3ENR = 0u; + RCC->APB1ENR = 0u; + RCC->APB2ENR = 0u; + RCC->AHB1LPENR = 0x7e6791ff; + RCC->AHB2LPENR = 0x000000f1; + RCC->AHB3LPENR = 0x00000001; + RCC->APB1LPENR = 0x36fec9ff; + RCC->APB2LPENR = 0x00075f33; + + /* Reset forgotten registers */ + RCC->BDCR = 0u; + RCC->CSR = 0x0e000000; + RCC->SSCGR = 0u; + RCC->DCKCFGR = 0u; +} + + +/* + * See header file + */ +void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status) +{ + volatile uint32_t *reg; + uint32_t bit_pos; + + /* Select correct enable register */ + switch (peripheral) { + /* AHB1 */ + case PER_GPIOA: + bit_pos = 0u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOB: + bit_pos = 1u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOC: + bit_pos = 2u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOD: + bit_pos = 3u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOE: + bit_pos = 4u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOF: + bit_pos = 5u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOG: + bit_pos = 6u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOH: + bit_pos = 7u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOI: + bit_pos = 8u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOJ: + bit_pos = 9u; + reg = &RCC->AHB1ENR; + break; + case PER_GPIOK: + bit_pos = 10u; + reg = &RCC->AHB1ENR; + break; + case PER_DMA1: + bit_pos = 21u; + reg = &RCC->AHB1ENR; + break; + case PER_DMA2: + bit_pos = 22u; + reg = &RCC->AHB1ENR; + break; + + /* AHB3 */ + case PER_FMC: + bit_pos = 0u; + reg = &RCC->AHB3ENR; + break; + + /* APB1 */ + case PER_DAC: + bit_pos = 29u; + reg = &RCC->APB1ENR; + break; + case PER_PWR: + bit_pos = 28u; + reg = &RCC->APB1ENR; + break; + case PER_TIM2: + bit_pos = 0u; + reg = &RCC->APB1ENR; + break; + case PER_TIM3: + bit_pos = 1u; + reg = &RCC->APB1ENR; + break; + case PER_TIM4: + bit_pos = 2u; + reg = &RCC->APB1ENR; + break; + case PER_TIM5: + bit_pos = 3u; + reg = &RCC->APB1ENR; + break; + + + /* APB2 */ + case PER_ADC1: + bit_pos = 8u; + reg = &RCC->APB2ENR; + break; + case PER_ADC2: + bit_pos = 9u; + reg = &RCC->APB2ENR; + break; + case PER_ADC3: + bit_pos = 10u; + reg = &RCC->APB2ENR; + break; + + default: + return; + } + + if (status == DISABLE) { + *reg &= ~(1u << bit_pos); + } else { + *reg |= (1u << bit_pos); + } +} + + +/* + * See header file + */ +hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status) +{ + uint32_t reg = 0; + uint32_t count = 0; + + /* Disable source */ + if (status == DISABLE) { + RCC->CR &= ~(1u << source); + return DISABLED; + } + + /* If pll, check if source is ok */ + if (source == HAL_RCC_OSC_PLL || + source == HAL_RCC_OSC_PLLI2S || + source == HAL_RCC_OSC_PLLSAI) + { + reg = RCC->CR; + /* HSE */ + if (RCC->PLLCFGR & ~(1u << 22u)) { + reg &= (1u << (HAL_RCC_OSC_HSE + 1u)); + } + /* HSI */ + else { + reg &= (1u << (HAL_RCC_OSC_HSI + 1u)); + } + /* Return if source is not ok */ + if (!reg) { + return DISABLED; + } + } + + /* Enable source */ + RCC->CR |= (1u << source); + + /* Wait till source is ready and if time out is reached exit */ + reg = RCC->CR & (1u << (source + 1u)); + while ((reg == 0) && (count != TIME_OUT)) { + reg = RCC->CR & (1u << (source + 1u)); + count++; + } + + /* Return */ + if (reg != 0) { + return ENABLED; + } + return DISABLED; +} + + +/* + * See header file + */ +void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init) +{ + /* Input check */ + if (init.m_divider < 2u) init.m_divider = 2u; + + if (init.n_factor < 2u) init.n_factor = 2u; + if (init.n_factor > 432u) init.n_factor = 432u; + + if (init.p_divider > 8u) init.p_divider = 8u; + + if (init.q_divider < 2u) init.q_divider = 2u; + + init.r_divider &= 0x07; + + /* Set source or return if invalid */ + if (init.source == HAL_RCC_OSC_HSI) { + RCC->PLLCFGR &= ~(1u << 22u); + } else if (init.source == HAL_RCC_OSC_HSE) { + RCC->PLLCFGR |= (1u << 22u); + } else { + return; + } + + /* Set pll preescaler */ + RCC->PLLCFGR &= ~(0x3f); + RCC->PLLCFGR |= init.m_divider; + + /* Configure pll */ + switch (pll) { + case HAL_RCC_OSC_PLL: + RCC->PLLCFGR &= ~0x0f037fc0; + RCC->PLLCFGR |= (init.n_factor << 6u); + RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u); + RCC->PLLCFGR |= (init.q_divider << 24u); + break; + + case HAL_RCC_OSC_PLLI2S: + RCC->PLLI2SCFGR &= ~0x7f007fc0; + RCC->PLLI2SCFGR |= (init.n_factor << 6u); + RCC->PLLI2SCFGR |= (init.q_divider << 24u); + RCC->PLLI2SCFGR |= (init.r_divider << 28u); + break; + +/* case HAL_RCC_OSC_PLLSAI: + RCC->PLLSAICFGR &= ~0x7f007fc0; + RCC->PLLSAICFGR |= (init.n_factor << 6u); + RCC->PLLSAICFGR |= (init.q_divider << 24u); + RCC->PLLSAICFGR |= (init.r_divider << 28u); + break; +*/ + default: + break; + } +} + + +/* + * See header file + */ +void hal_rcc_setup_clock(hal_rcc_clk_init_t init) +{ + uint32_t reg = 0; + + /* Configure clock divider */ + RCC->CFGR &= ~0x0000fcf0; + RCC->CFGR |= (init.hpre << 4u); + RCC->CFGR |= (init.ppre1 << 10u); + RCC->CFGR |= (init.ppre2 << 13u); + + /* Select system clock source */ + RCC->CFGR &= ~0x00000003; + switch (init.osc) { + default: + case HAL_RCC_OSC_HSI: + reg = 0u; + break; + + case HAL_RCC_OSC_HSE: + reg = 1u; + break; + + case HAL_RCC_OSC_PLL: + reg = 2u; + break; + } + RCC->CFGR |= reg; + +#ifndef TESTING + /* Wait till system clock is selected */ + while ((RCC->CFGR & 0x0000000c) != (reg << 2u)); +#endif +} diff --git a/CT-Lab1-Project/RTE/_Target_1/RTE_Components.h b/CT-Lab1-Project/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..a26857a --- /dev/null +++ b/CT-Lab1-Project/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,15 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'CT-Lab1-Project' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/CT-Lab1-Project/app/task.c b/CT-Lab1-Project/app/task.c new file mode 100644 index 0000000..c15f8cc --- /dev/null +++ b/CT-Lab1-Project/app/task.c @@ -0,0 +1,97 @@ +#include "utils_ctboard.h" + +uint8_t getData7Segment(uint8_t digit); +uint16_t getData7SegmentTwoDigits(uint8_t digit); + +int main(void) { + /* initializations go here */ + uint8_t rotationSwitchData; + while (1) { + /*Connect LEDs to Switchs */ + write_word(0x60000100, read_word(0x60000200)); + /*Connect Rotation Switch to 7 Segment */ + rotationSwitchData = read_byte(0x60000211) & 0x0F; + /*write_word(0x60000110, getData7Segment(rotationSwitchData) | 0xFFFF0000); */ + write_byte(0x60000110, getData7Segment(rotationSwitchData)); + } +} + +uint8_t getData7Segment(uint8_t digit) { + switch(digit) { + case 0x0: + return 0xC0; + case 0x1: + return 0xF9; + case 0x2: + return 0xA4; + case 0x3: + return 0xB0; + case 0x4: + return 0x99; + case 0x5: + return 0x92; + case 0x6: + return 0x82; + case 0x7: + return 0xF8; + case 0x8: + return 0x80; + case 0x9: + return 0x90; + case 0xA: + return 0x88; + case 0xB: + return 0x83; + case 0xC: + return 0xC6; + case 0xD: + return 0xA1; + case 0xE: + return 0x86; + case 0xF: + return 0x8E; + default: + return 0xFF; + + } +} + +uint16_t getData7SegmentTwoDigits(uint8_t digit) { + switch(digit) { + case 0x0: + return 0xFFC0; + case 0x1: + return 0xFFF9; + case 0x2: + return 0xFFA4; + case 0x3: + return 0xFFB0; + case 0x4: + return 0xFF99; + case 0x5: + return 0xFF92; + case 0x6: + return 0xFF82; + case 0x7: + return 0xFFF8; + case 0x8: + return 0xFF80; + case 0x9: + return 0xFF90; + case 0xA: + return 0xF9C0; + case 0xB: + return 0xF9F9; + case 0xC: + return 0xF9A4; + case 0xD: + return 0xF9B0; + case 0xE: + return 0xF999; + case 0xF: + return 0xF992; + default: + return 0xFFFF; + + } +} diff --git a/CT-Lab1-Project/app/utils_ctboard.c b/CT-Lab1-Project/app/utils_ctboard.c new file mode 100644 index 0000000..5c4e1eb --- /dev/null +++ b/CT-Lab1-Project/app/utils_ctboard.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ---------------------------------------------------------------------------- + * -- + * -- Project : CT Board - Cortex M4 + * -- Description : Utilities for ct board. + * -- + * -- $Id: utils_ctboard.c 2160 2015-06-08 12:28:00Z feur $ + * ------------------------------------------------------------------------- */ + +#include +#include "utils_ctboard.h" + +/* ---------------------------------------------------------------------------- + * -- Functions + * ---------------------------------------------------------------------------- + */ + +/* + * See header file + */ +uint8_t read_byte(uint32_t address) +{ + uint8_t *pointer; + pointer = (uint8_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint16_t read_halfword(uint32_t address) +{ + uint16_t *pointer; + pointer = (uint16_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint32_t read_word(uint32_t address) +{ + uint32_t *pointer; + pointer = (uint32_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint64_t read_doubleword(uint32_t address) +{ + uint64_t *pointer; + pointer = (uint64_t *)address; + return *pointer; +} + + +/* + * See header file + */ +void write_byte(uint32_t address, uint8_t data) +{ + uint8_t *pointer; + pointer = (uint8_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_halfword(uint32_t address, uint16_t data) +{ + uint16_t *pointer; + pointer = (uint16_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_word(uint32_t address, uint32_t data) +{ + uint32_t *pointer; + pointer = (uint32_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_doubleword(uint32_t address, uint64_t data) +{ + uint64_t *pointer; + pointer = (uint64_t *)address; + *pointer = data; +} diff --git a/CT-Lab1-Project/app/utils_ctboard.h b/CT-Lab1-Project/app/utils_ctboard.h new file mode 100644 index 0000000..b946a56 --- /dev/null +++ b/CT-Lab1-Project/app/utils_ctboard.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ---------------------------------------------------------------------------- + * -- + * -- Module : ctboard_utils + * -- Description : Interface for module. + * -- + * -- $Id: utils_ctboard.h 1122 2015-01-06 13:57:04Z feur $ + * ------------------------------------------------------------------------- */ +#ifndef _UTILS_CTBOARD +#define _UTILS_CTBOARD + +#include + +/* ---------------------------------------------------------------------------- + * -- Function prototypes + * ---------------------------------------------------------------------------- + */ + +/* + * Functions to read either a byte, halfword, word or + * doubleword from an arbitrary address. + * @param address: address to read from (32 bit) + * @retval data @ address + */ +uint8_t read_byte(uint32_t address); +uint16_t read_halfword(uint32_t address); +uint32_t read_word(uint32_t address); +uint64_t read_doubleword(uint32_t address); + + +/* + * Functions to write either a byte, halfword, word or + * doubleword to an arbitrary address. + * @param address: address to write to (32 bit) + * data: data to write @ address + */ +void write_byte(uint32_t address, uint8_t data); +void write_halfword(uint32_t address, uint16_t data); +void write_word(uint32_t address, uint32_t data); +void write_doubleword(uint32_t address, uint64_t data); + +/* ---------------------------------------------------------------------------- + * -- Header file end + * ---------------------------------------------------------------------------- + */ +#endif diff --git a/CT-Lab1-Project/build/CT-Lab1-Project.axf b/CT-Lab1-Project/build/CT-Lab1-Project.axf new file mode 100644 index 0000000..f047779 Binary files /dev/null and b/CT-Lab1-Project/build/CT-Lab1-Project.axf differ diff --git a/CT-Lab1-Project/build/CT-Lab1-Project.build_log.htm b/CT-Lab1-Project/build/CT-Lab1-Project.build_log.htm new file mode 100644 index 0000000..12f0988 --- /dev/null +++ b/CT-Lab1-Project/build/CT-Lab1-Project.build_log.htm @@ -0,0 +1,335 @@ + + +
+
µVision Build Log

+
Tool Versions:

+IDE-Version: µVision V5.37.0.0
+Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Roman Schenk, ZHAW, LIC=----
+ 
+Tool Versions:
+Toolchain:       MDK-Lite  Version: 5.37.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.18
+Assembler:       Armasm.exe V6.18
+Linker/Locator:  ArmLink.exe V6.18
+Library Manager: ArmAr.exe V6.18
+Hex Converter:   FromElf.exe V6.18
+CPU DLL:         SARMCM3.DLL V5.37.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.6.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V3.0.9.0
+Dialog DLL:      TARMCM1.DLL V1.14.6.0
+ 
+
Project:

+C:\Users\roman\Documents\CT-Lab1-Project\CT-Lab1-Project.uvprojx
+Project File Date:  09/23/2022
+
+
Output:

+*** Using Compiler 'V6.18', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
+Rebuild target 'Target 1'
+assembling startup_ctboard.s...
+assembling datainit_ctboard.s...
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(32): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(24): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(1181): warning: // comments are not allowed in this language [-Wcomment]
+//    volatile uint32_t HR[5];
+^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(32): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(25): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include/hal_common.h(59): warning: // comments are not allowed in this language [-Wcomment]
+    PER_ADC1,       // APB2
+                    ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(32): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(168): warning: commas at the end of enumerator lists are a C99-specific feature [-Wc99-extensions]
+    HAL_GPIO_PIN_All = 0xffff,
+                             ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(33): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_fmc.h(71): warning: commas at the end of enumerator lists are a C99-specific feature [-Wc99-extensions]
+    HAL_FMC_ACCESS_MODE_D = 3u,     /**< Access mode D. */
+                              ^~
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(77): warning: no previous prototype for function '__system' [-Wmissing-prototypes]
+void __system(void)
+     ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(77): note: declare 'static' if the function is not intended to be used outside of this translation unit
+void __system(void)
+^
+static 
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(105): warning: unused parameter 'entry' [-Wunused-parameter]
+void system_enter_sleep(hal_pwr_lp_entry_t entry)
+                                           ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(114): warning: unused parameter 'regulator' [-Wunused-parameter]
+void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
+                                           ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(114): warning: unused parameter 'entry' [-Wunused-parameter]
+void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
+                                                                         ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(146): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    PWR_RESET();
+    ^~~~~~~~~~~
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(178): note: expanded from macro 'PWR_RESET'
+#define PWR_RESET()             REG_TGL(RCC->APB1RSTR,  PWR_RCC_PATTERN)
+                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(31): note: expanded from macro 'REG_TGL'
+                                    REG_CLR((REG), (BIT));  \
+                                    ^~~~~~~~~~~~~~~~~~~~~
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(26): note: expanded from macro 'REG_CLR'
+#define REG_CLR(REG, BIT)       ( (REG) &= ~(BIT) )
+                                        ~~ ^~~~~~
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(35): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_rcc.h(78): warning: padding struct 'hal_rcc_pll_init_t' with 1 byte to align 'n_factor' [-Wpadded]
+    uint16_t n_factor;
+             ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(174): warning: // comments are not allowed in this language [-Wcomment]
+        clk_init.hpre = HAL_RCC_HPRE_2;     // -> AHB clock : 84 MHz
+                                            ^
+RTE/Device/CT_Board_HS14_M0/system_ctboard.c(42): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\system_ctboard.h(32): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(197): warning: padding size of 'hal_gpio_output_t' with 1 byte to alignment boundary [-Wpadded]
+typedef struct {
+        ^
+12 warnings generated.
+compiling system_ctboard.c...
+compiling utils_ctboard.c...
+compiling task.c...
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_fmc.h(24): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include/hal_common.h(59): warning: // comments are not allowed in this language [-Wcomment]
+    PER_ADC1,       // APB2
+                    ^
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_fmc.h(71): warning: commas at the end of enumerator lists are a C99-specific feature [-Wc99-extensions]
+    HAL_FMC_ACCESS_MODE_D = 3u,     /**< Access mode D. */
+                              ^~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(19): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(1181): warning: // comments are not allowed in this language [-Wcomment]
+//    volatile uint32_t HR[5];
+^
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(38): warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
+        default:
+        ^
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(82): warning: // comments are not allowed in this language [-Wcomment]
+    timing.clk_divider -= 1u;  // 0b0001 -> clk / 2
+                               ^
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(97): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    reg_cr |= (init.type << 2u);
+           ~~  ~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(98): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    reg_cr |= (init.width << 4u);
+           ~~  ~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(102): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.address_setup << 0u);
+               ~~  ~~~~~~~~~~~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(103): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.address_hold << 4u);
+               ~~  ~~~~~~~~~~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(104): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.data_setup << 8u);
+               ~~  ~~~~~~~~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(105): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.mode << 28u);
+               ~~  ~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(109): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.clk_divider << 20u);
+               ~~  ~~~~~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(110): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+        reg_tr |= (timing.data_latency << 24u);
+               ~~  ~~~~~~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(113): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    reg_tr |= (timing.bus_turnaround << 16u);
+           ~~  ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_fmc.c(117): warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
+        default:
+        ^
+15 warnings generated.
+compiling hal_fmc.c...
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(24): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(1181): warning: // comments are not allowed in this language [-Wcomment]
+//    volatile uint32_t HR[5];
+^
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(25): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include/hal_common.h(59): warning: // comments are not allowed in this language [-Wcomment]
+    PER_ADC1,       // APB2
+                    ^
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(168): warning: commas at the end of enumerator lists are a C99-specific feature [-Wc99-extensions]
+    HAL_GPIO_PIN_All = 0xffff,
+                             ^
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(187): warning: padding size of 'hal_gpio_input_t' with 1 byte to alignment boundary [-Wpadded]
+typedef struct {
+        ^
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_gpio.h(197): warning: padding size of 'hal_gpio_output_t' with 1 byte to alignment boundary [-Wpadded]
+typedef struct {
+        ^
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(207): warning: implicit conversion changes signedness: 'int' to 'uint32_t' (aka 'unsigned int') [-Wsign-conversion]
+        port->BSRR = (pins << 16);
+                   ~  ~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(264): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+                    SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
+                                    ~~ ^~~~~~~~~~~~~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(267): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+                    SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
+                                    ~~ ^~~~~~~~~~~~~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(270): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+                    SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
+                                    ~~ ^~~~~~~~~~~~~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(273): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+                    SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
+                                    ~~ ^~~~~~~~~~~~~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_gpio.c(366): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+                mask |= pattern << (pos * pattern_bit_width);
+                     ~~ ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~
+11 warnings generated.
+compiling hal_gpio.c...
+RTE/HAL/CT_Board_HS14_M0/hal_pwr.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_pwr.h(24): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include/hal_common.h(59): warning: // comments are not allowed in this language [-Wcomment]
+    PER_ADC1,       // APB2
+                    ^
+RTE/HAL/CT_Board_HS14_M0/hal_pwr.c(19): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(1181): warning: // comments are not allowed in this language [-Wcomment]
+//    volatile uint32_t HR[5];
+^
+RTE/HAL/CT_Board_HS14_M0/hal_pwr.c(117): warning: unused parameter 'status' [-Wunused-parameter]
+hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
+                                            ^
+RTE/HAL/CT_Board_HS14_M0/hal_pwr.c(128): warning: unused parameter 'status' [-Wunused-parameter]
+hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
+                                             ^
+4 warnings generated.
+compiling hal_pwr.c...
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_rcc.h(24): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include/hal_common.h(59): warning: // comments are not allowed in this language [-Wcomment]
+    PER_ADC1,       // APB2
+                    ^
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(19): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include\reg_stm32f4xx.h(1181): warning: // comments are not allowed in this language [-Wcomment]
+//    volatile uint32_t HR[5];
+^
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(37): warning: // comments are not allowed in this language [-Wcomment]
+    RCC->CR |= 0x00000001;   // Set HSION bit first -> keep cpu running
+                             ^
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(189): warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
+        default:
+        ^
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(18): warning: In file included from...
+C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include\hal_rcc.h(78): warning: padding struct 'hal_rcc_pll_init_t' with 1 byte to align 'n_factor' [-Wpadded]
+    uint16_t n_factor;
+             ^
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(280): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->PLLCFGR &= ~(0x3f);
+                 ~~ ^~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(286): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLCFGR &= ~0x0f037fc0;
+                         ~~ ^~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(287): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLCFGR |= (init.n_factor << 6u);
+                         ~~  ~~~~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(288): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
+                         ~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(289): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLCFGR |= (init.q_divider << 24u);
+                         ~~  ~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(293): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLI2SCFGR &= ~0x7f007fc0;
+                            ~~ ^~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(294): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLI2SCFGR |= (init.n_factor << 6u);
+                            ~~  ~~~~~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(295): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLI2SCFGR |= (init.q_divider << 24u);
+                            ~~  ~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(296): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+            RCC->PLLI2SCFGR |= (init.r_divider << 28u);
+                            ~~  ~~~~~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(284): warning: enumeration values 'HAL_RCC_OSC_HSI', 'HAL_RCC_OSC_HSE', and 'HAL_RCC_OSC_PLLSAI' not explicitly handled in switch [-Wswitch-enum]
+    switch (pll) {
+            ^~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(320): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->CFGR &= ~0x0000fcf0;
+              ~~ ^~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(321): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->CFGR |= (init.hpre << 4u);
+              ~~  ~~~~~~~~~~^~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(322): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->CFGR |= (init.ppre1 << 10u);
+              ~~  ~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(323): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->CFGR |= (init.ppre2 << 13u);
+              ~~  ~~~~~~~~~~~^~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(326): warning: implicit conversion changes signedness: 'int' to 'unsigned int' [-Wsign-conversion]
+    RCC->CFGR &= ~0x00000003;
+              ~~ ^~~~~~~~~~~
+RTE/HAL/CT_Board_HS14_M0/hal_rcc.c(327): warning: enumeration values 'HAL_RCC_OSC_PLLI2S' and 'HAL_RCC_OSC_PLLSAI' not explicitly handled in switch [-Wswitch-enum]
+    switch (init.osc) {
+            ^~~~~~~~
+21 warnings generated.
+compiling hal_rcc.c...
+linking...
+Program Size: Code=3852 RO-data=428 RW-data=0 ZI-data=8192  
+".\build\CT-Lab1-Project.axf" - 0 Error(s), 63 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: InES
+                https://ennis.zhaw.ch/pack/InES.CTBoard14_DFP.4.0.2.pack
+                InES.CTBoard14_DFP.4.0.2
+                CT Board 14 (STM32F429ZI) Device Support
+   * Component: Startup Version: 4.0.1
+   * Component: FMC Version: 3.0.1
+   * Component: GPIO Version: 4.0.1
+   * Component: PWR Version: 2.2.0
+   * Component: RCC Version: 4.0.1
+
+
Collection of Component include folders:

+  ./RTE/_Target_1
+  C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
+  C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
+  C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
+
+
Collection of Component Files used:

+
+   * Component: InES::Device:Startup:4.0.1
+      Include file:  Device/Include/reg_stm32f4xx.h
+      Include file:  Device/Include/reg_ctboard.h
+      Include file:  Device/Include/m0/platform_ctboard.h
+      Include file:  Device/Include/system_ctboard.h
+      Source file:   Device/Source/system_ctboard.c
+      Source file:   Device/Source/datainit_ctboard.s
+      Source file:   Device/Source/startup_ctboard.s
+
+   * Component: InES::HAL:FMC:3.0.1
+      Source file:   HAL/Source/hal_fmc.c
+      Include file:  HAL/Include/hal_common.h
+      Include file:  HAL/Include/hal_fmc.h
+      Include file:  Device/Include/reg_stm32f4xx.h
+
+   * Component: InES::HAL:GPIO:4.0.1
+      Include file:  HAL/Include/hal_gpio.h
+      Include file:  Device/Include/reg_stm32f4xx.h
+      Source file:   HAL/Source/hal_gpio.c
+      Include file:  HAL/Include/hal_common.h
+
+   * Component: InES::HAL:PWR:2.2.0
+      Include file:  Device/Include/reg_stm32f4xx.h
+      Source file:   HAL/Source/hal_pwr.c
+      Include file:  HAL/Include/hal_common.h
+      Include file:  HAL/Include/hal_pwr.h
+
+   * Component: InES::HAL:RCC:4.0.1
+      Source file:   HAL/Source/hal_rcc.c
+      Include file:  HAL/Include/hal_common.h
+      Include file:  HAL/Include/hal_rcc.h
+      Include file:  Device/Include/reg_stm32f4xx.h
+Build Time Elapsed:  00:00:01
+
+ + diff --git a/CT-Lab1-Project/build/CT-Lab1-Project.htm b/CT-Lab1-Project/build/CT-Lab1-Project.htm new file mode 100644 index 0000000..e96b21c --- /dev/null +++ b/CT-Lab1-Project/build/CT-Lab1-Project.htm @@ -0,0 +1,656 @@ + + +Static Call Graph - [.\build\CT-Lab1-Project.axf] +
+

Static Call Graph for image .\build\CT-Lab1-Project.axf

+

#<CALLGRAPH># ARM Linker, 6180002: Last Updated: Fri Sep 30 07:35:31 2022 +

+

Maximum Stack Usage = 312 bytes + Unknown(Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__system ⇒ system_enter_run ⇒ init_FMC_SRAM ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output ⇒ create_pattern_mask +

+

+Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • MemManage_Handler   ⇒   MemManage_Handler
    +
  • BusFault_Handler   ⇒   BusFault_Handler
    +
  • UsageFault_Handler   ⇒   UsageFault_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • DebugMon_Handler   ⇒   DebugMon_Handler
    +
  • PendSV_Handler   ⇒   PendSV_Handler
    +
  • SysTick_Handler   ⇒   SysTick_Handler
    +
  • ADC_IRQHandler   ⇒   ADC_IRQHandler
    + +

    +

    +Function Pointers +

      +
    • ADC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • BusFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN1_RX0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN1_RX1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN1_SCE_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN1_TX_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN2_RX0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN2_RX1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN2_SCE_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CAN2_TX_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • CRYP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DCMI_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA1_Stream7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2D_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DMA2_Stream7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • DebugMon_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • ETH_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • ETH_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI15_10_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • EXTI9_5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • FLASH_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • FMC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • FPU_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • HASH_RNG_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • HardFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C1_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C1_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C2_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C2_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C3_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • I2C3_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • LTDC_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • LTDC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • MemManage_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • NMI_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_FS_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_FS_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_HS_EP1_IN_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_HS_EP1_OUT_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_HS_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • OTG_HS_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • PVD_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • PendSV_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • RCC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • RTC_Alarm_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • RTC_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • Reset_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SAI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SDIO_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SPI6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SVC_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • SysTick_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TAMP_STAMP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM1_BRK_TIM9_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM1_CC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM1_TRG_COM_TIM11_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM1_UP_TIM10_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM6_DAC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM8_BRK_TIM12_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM8_CC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM8_TRG_COM_TIM14_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • TIM8_UP_TIM13_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • UART4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • UART5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • UART7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • UART8_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • USART1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • USART2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • USART3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • USART6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • UsageFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • WWDG_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET) +
    • __main from datainit_ctboard.o(.text) referenced from startup_ctboard.o(.text) +
    • __system from system_ctboard.o(.text.__system) referenced from startup_ctboard.o(.text) +
    • main from task.o(.text.main) referenced from datainit_ctboard.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 74 bytes, Stack size 0 bytes, datainit_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(.text) +
    +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   DebugMon_Handler +
    +
    [Called By]
    • >>   DebugMon_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   SysTick_Handler +
    +
    [Called By]
    • >>   SysTick_Handler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +

    [Calls]

    • >>   ADC_IRQHandler +
    +
    [Called By]
    • >>   ADC_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(RESET) +
    +

    CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    CRYP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2D_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    HASH_RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    LTDC_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    LTDC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    SPI6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    UART7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    UART8_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text)) +
    [Address Reference Count : 1]

    • startup_ctboard.o(RESET) +
    +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text)) +

    [Called By]

    • >>   create_pattern_mask +
    + +

    __aeabi_uidivmod (Thumb, 20 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 338 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __system (Thumb, 8 bytes, Stack size 8 bytes, system_ctboard.o(.text.__system)) +

    [Stack]

    • Max Depth = 312
    • Call Chain = __system ⇒ system_enter_run ⇒ init_FMC_SRAM ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output ⇒ create_pattern_mask +
    +
    [Calls]
    • >>   system_enter_run +
    +
    [Address Reference Count : 1]
    • startup_ctboard.o(.text) +
    +

    getData7Segment (Thumb, 236 bytes, Stack size 12 bytes, task.o(.text.getData7Segment)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = getData7Segment +
    +
    [Called By]
    • >>   main +
    + +

    hal_fmc_init_sram (Thumb, 564 bytes, Stack size 64 bytes, hal_fmc.o(.text.hal_fmc_init_sram)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = hal_fmc_init_sram +
    +
    [Called By]
    • >>   init_FMC_SRAM +
    + +

    hal_gpio_init_alternate (Thumb, 194 bytes, Stack size 72 bytes, hal_gpio.o(.text.hal_gpio_init_alternate)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = hal_gpio_init_alternate ⇒ hal_gpio_init_output ⇒ create_pattern_mask +
    +
    [Calls]
    • >>   hal_gpio_init_output +
    • >>   create_pattern_mask +
    +
    [Called By]
    • >>   init_FMC_SRAM +
    + +

    hal_gpio_init_output (Thumb, 208 bytes, Stack size 48 bytes, hal_gpio.o(.text.hal_gpio_init_output)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = hal_gpio_init_output ⇒ create_pattern_mask +
    +
    [Calls]
    • >>   create_pattern_mask +
    • >>   intercept_overwrite_register +
    +
    [Called By]
    • >>   hal_gpio_init_alternate +
    + +

    hal_pwr_set_overdrive (Thumb, 12 bytes, Stack size 4 bytes, hal_pwr.o(.text.hal_pwr_set_overdrive)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = hal_pwr_set_overdrive +
    +
    [Called By]
    • >>   init_SystemClock +
    + +

    hal_rcc_reset (Thumb, 148 bytes, Stack size 0 bytes, hal_rcc.o(.text.hal_rcc_reset)) +

    [Called By]

    • >>   init_SystemClock +
    + +

    hal_rcc_set_osc (Thumb, 268 bytes, Stack size 32 bytes, hal_rcc.o(.text.hal_rcc_set_osc)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_rcc_set_osc +
    +
    [Called By]
    • >>   init_SystemClock +
    + +

    hal_rcc_setup_clock (Thumb, 160 bytes, Stack size 20 bytes, hal_rcc.o(.text.hal_rcc_setup_clock)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = hal_rcc_setup_clock +
    +
    [Called By]
    • >>   init_SystemClock +
    + +

    hal_rcc_setup_pll (Thumb, 328 bytes, Stack size 24 bytes, hal_rcc.o(.text.hal_rcc_setup_pll)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_rcc_setup_pll +
    +
    [Called By]
    • >>   init_SystemClock +
    + +

    main (Thumb, 56 bytes, Stack size 16 bytes, task.o(.text.main)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = main ⇒ getData7Segment +
    +
    [Calls]
    • >>   getData7Segment +
    • >>   write_word +
    • >>   write_byte +
    • >>   read_word +
    • >>   read_byte +
    +
    [Address Reference Count : 1]
    • datainit_ctboard.o(.text) +
    +

    read_byte (Thumb, 16 bytes, Stack size 8 bytes, utils_ctboard.o(.text.read_byte)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = read_byte +
    +
    [Called By]
    • >>   main +
    + +

    read_word (Thumb, 16 bytes, Stack size 8 bytes, utils_ctboard.o(.text.read_word)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = read_word +
    +
    [Called By]
    • >>   main +
    + +

    system_enter_run (Thumb, 20 bytes, Stack size 8 bytes, system_ctboard.o(.text.system_enter_run)) +

    [Stack]

    • Max Depth = 304
    • Call Chain = system_enter_run ⇒ init_FMC_SRAM ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output ⇒ create_pattern_mask +
    +
    [Calls]
    • >>   init_LCD +
    • >>   init_FMC_SRAM +
    • >>   init_FPU +
    • >>   init_SystemClock +
    +
    [Called By]
    • >>   __system +
    + +

    write_byte (Thumb, 22 bytes, Stack size 12 bytes, utils_ctboard.o(.text.write_byte)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = write_byte +
    +
    [Called By]
    • >>   main +
    + +

    write_word (Thumb, 20 bytes, Stack size 12 bytes, utils_ctboard.o(.text.write_word)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = write_word +
    +
    [Called By]
    • >>   main +
    +

    +

    +Local Symbols +

    +

    init_SystemClock (Thumb, 196 bytes, Stack size 40 bytes, system_ctboard.o(.text.init_SystemClock)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = init_SystemClock ⇒ hal_rcc_set_osc +
    +
    [Calls]
    • >>   hal_rcc_setup_clock +
    • >>   hal_pwr_set_overdrive +
    • >>   hal_rcc_setup_pll +
    • >>   hal_rcc_set_osc +
    • >>   hal_rcc_reset +
    +
    [Called By]
    • >>   system_enter_run +
    + +

    init_FPU (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text.init_FPU)) +

    [Called By]

    • >>   system_enter_run +
    + +

    init_FMC_SRAM (Thumb, 340 bytes, Stack size 136 bytes, system_ctboard.o(.text.init_FMC_SRAM)) +

    [Stack]

    • Max Depth = 296
    • Call Chain = init_FMC_SRAM ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output ⇒ create_pattern_mask +
    +
    [Calls]
    • >>   hal_fmc_init_sram +
    • >>   hal_gpio_init_alternate +
    +
    [Called By]
    • >>   system_enter_run +
    + +

    init_LCD (Thumb, 32 bytes, Stack size 4 bytes, system_ctboard.o(.text.init_LCD)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = init_LCD +
    +
    [Called By]
    • >>   system_enter_run +
    + +

    intercept_overwrite_register (Thumb, 48 bytes, Stack size 8 bytes, hal_gpio.o(.text.intercept_overwrite_register)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = intercept_overwrite_register +
    +
    [Called By]
    • >>   hal_gpio_init_output +
    + +

    create_pattern_mask (Thumb, 156 bytes, Stack size 40 bytes, hal_gpio.o(.text.create_pattern_mask)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = create_pattern_mask +
    +
    [Calls]
    • >>   __aeabi_uidiv +
    +
    [Called By]
    • >>   hal_gpio_init_output +
    • >>   hal_gpio_init_alternate +
    +

    +

    +Undefined Global Symbols +

    diff --git a/CT-Lab1-Project/build/CT-Lab1-Project.lnp b/CT-Lab1-Project/build/CT-Lab1-Project.lnp new file mode 100644 index 0000000..9c2056c --- /dev/null +++ b/CT-Lab1-Project/build/CT-Lab1-Project.lnp @@ -0,0 +1,14 @@ +--cpu Cortex-M0 +".\build\utils_ctboard.o" +".\build\task.o" +".\build\datainit_ctboard.o" +".\build\startup_ctboard.o" +".\build\system_ctboard.o" +".\build\hal_fmc.o" +".\build\hal_gpio.o" +".\build\hal_pwr.o" +".\build\hal_rcc.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict +--diag_suppress 6314 --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\CT-Lab1-Project.map" -o .\build\CT-Lab1-Project.axf \ No newline at end of file diff --git a/CT-Lab1-Project/build/CT-Lab1-Project_Target 1.dep b/CT-Lab1-Project/build/CT-Lab1-Project_Target 1.dep new file mode 100644 index 0000000..f43160b --- /dev/null +++ b/CT-Lab1-Project/build/CT-Lab1-Project_Target 1.dep @@ -0,0 +1,41 @@ +Dependencies for Project 'CT-Lab1-Project', Target 'Target 1': (DO NOT MODIFY !) +CompilerVersion: 6180000::V6.18::ARMCLANG +F (.\app\utils_ctboard.c)(0x613F3541)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/utils_ctboard.o -MD) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (app\utils_ctboard.h)(0x613F3541) +F (.\app\task.c)(0x63368018)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/task.o -MD) +I (app\utils_ctboard.h)(0x613F3541) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +F (RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s)(0x5C517478)(--target=arm-arm-none-eabi -mcpu=cortex-m0 -masm=auto -c -gdwarf-4 -Wa,armasm,--pd,"__EVAL SETA 1" -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -Wa,armasm,--pd,"__UVISION_VERSION SETA 537" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -o ./build/datainit_ctboard.o) +F (RTE/Device/CT_Board_HS14_M0/startup_ctboard.s)(0x5C517478)(--target=arm-arm-none-eabi -mcpu=cortex-m0 -masm=auto -c -gdwarf-4 -Wa,armasm,--pd,"__EVAL SETA 1" -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -Wa,armasm,--pd,"__UVISION_VERSION SETA 537" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -o ./build/startup_ctboard.o) +F (RTE/Device/CT_Board_HS14_M0/system_ctboard.c)(0x5C597514)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/system_ctboard.o -MD) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h)(0x5C6AA868) +F (RTE/HAL/CT_Board_HS14_M0/hal_fmc.c)(0x5C517478)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_fmc.o -MD) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514) +F (RTE/HAL/CT_Board_HS14_M0/hal_gpio.c)(0x5C5ACEB0)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_gpio.o -MD) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478) +F (RTE/HAL/CT_Board_HS14_M0/hal_pwr.c)(0x5C517478)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_pwr.o -MD) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514) +F (RTE/HAL/CT_Board_HS14_M0/hal_rcc.c)(0x5C597514)(-xc -std=c90 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O0 -ffunction-sections -Weverything -Wno-packed -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_rcc.o -MD) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478) +I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538) +I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514) diff --git a/CT-Lab1-Project/build/ExtDll.iex b/CT-Lab1-Project/build/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/CT-Lab1-Project/build/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/CT-Lab1-Project/build/datainit_ctboard.o b/CT-Lab1-Project/build/datainit_ctboard.o new file mode 100644 index 0000000..e848896 Binary files /dev/null and b/CT-Lab1-Project/build/datainit_ctboard.o differ diff --git a/CT-Lab1-Project/build/hal_fmc.d b/CT-Lab1-Project/build/hal_fmc.d new file mode 100644 index 0000000..7361834 --- /dev/null +++ b/CT-Lab1-Project/build/hal_fmc.d @@ -0,0 +1,5 @@ +./build/hal_fmc.o: RTE\HAL\CT_Board_HS14_M0\hal_fmc.c \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h diff --git a/CT-Lab1-Project/build/hal_fmc.o b/CT-Lab1-Project/build/hal_fmc.o new file mode 100644 index 0000000..372189e Binary files /dev/null and b/CT-Lab1-Project/build/hal_fmc.o differ diff --git a/CT-Lab1-Project/build/hal_gpio.d b/CT-Lab1-Project/build/hal_gpio.d new file mode 100644 index 0000000..48c4242 --- /dev/null +++ b/CT-Lab1-Project/build/hal_gpio.d @@ -0,0 +1,5 @@ +./build/hal_gpio.o: RTE\HAL\CT_Board_HS14_M0\hal_gpio.c \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h diff --git a/CT-Lab1-Project/build/hal_gpio.o b/CT-Lab1-Project/build/hal_gpio.o new file mode 100644 index 0000000..6e6717b Binary files /dev/null and b/CT-Lab1-Project/build/hal_gpio.o differ diff --git a/CT-Lab1-Project/build/hal_pwr.d b/CT-Lab1-Project/build/hal_pwr.d new file mode 100644 index 0000000..5a8be71 --- /dev/null +++ b/CT-Lab1-Project/build/hal_pwr.d @@ -0,0 +1,5 @@ +./build/hal_pwr.o: RTE\HAL\CT_Board_HS14_M0\hal_pwr.c \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h diff --git a/CT-Lab1-Project/build/hal_pwr.o b/CT-Lab1-Project/build/hal_pwr.o new file mode 100644 index 0000000..b6d6f03 Binary files /dev/null and b/CT-Lab1-Project/build/hal_pwr.o differ diff --git a/CT-Lab1-Project/build/hal_rcc.d b/CT-Lab1-Project/build/hal_rcc.d new file mode 100644 index 0000000..184a1d5 --- /dev/null +++ b/CT-Lab1-Project/build/hal_rcc.d @@ -0,0 +1,5 @@ +./build/hal_rcc.o: RTE\HAL\CT_Board_HS14_M0\hal_rcc.c \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h diff --git a/CT-Lab1-Project/build/hal_rcc.o b/CT-Lab1-Project/build/hal_rcc.o new file mode 100644 index 0000000..d2a4a3c Binary files /dev/null and b/CT-Lab1-Project/build/hal_rcc.o differ diff --git a/CT-Lab1-Project/build/startup_ctboard.o b/CT-Lab1-Project/build/startup_ctboard.o new file mode 100644 index 0000000..6d30a75 Binary files /dev/null and b/CT-Lab1-Project/build/startup_ctboard.o differ diff --git a/CT-Lab1-Project/build/system_ctboard.d b/CT-Lab1-Project/build/system_ctboard.d new file mode 100644 index 0000000..556de8b --- /dev/null +++ b/CT-Lab1-Project/build/system_ctboard.d @@ -0,0 +1,11 @@ +./build/system_ctboard.o: RTE\Device\CT_Board_HS14_M0\system_ctboard.c \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \ + C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h diff --git a/CT-Lab1-Project/build/system_ctboard.o b/CT-Lab1-Project/build/system_ctboard.o new file mode 100644 index 0000000..0d7826f Binary files /dev/null and b/CT-Lab1-Project/build/system_ctboard.o differ diff --git a/CT-Lab1-Project/build/task.d b/CT-Lab1-Project/build/task.d new file mode 100644 index 0000000..077f6b4 --- /dev/null +++ b/CT-Lab1-Project/build/task.d @@ -0,0 +1,2 @@ +./build/task.o: app\task.c app\utils_ctboard.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h diff --git a/CT-Lab1-Project/build/task.o b/CT-Lab1-Project/build/task.o new file mode 100644 index 0000000..6b3a6a8 Binary files /dev/null and b/CT-Lab1-Project/build/task.o differ diff --git a/CT-Lab1-Project/build/utils_ctboard.d b/CT-Lab1-Project/build/utils_ctboard.d new file mode 100644 index 0000000..44fca61 --- /dev/null +++ b/CT-Lab1-Project/build/utils_ctboard.d @@ -0,0 +1,2 @@ +./build/utils_ctboard.o: app\utils_ctboard.c \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h app\utils_ctboard.h diff --git a/CT-Lab1-Project/build/utils_ctboard.o b/CT-Lab1-Project/build/utils_ctboard.o new file mode 100644 index 0000000..5d38d08 Binary files /dev/null and b/CT-Lab1-Project/build/utils_ctboard.o differ diff --git a/CTP_TargetSystem.pdf b/CTP_TargetSystem.pdf new file mode 100644 index 0000000..62b85a1 Binary files /dev/null and b/CTP_TargetSystem.pdf differ diff --git a/utils_ctboard.c b/utils_ctboard.c new file mode 100644 index 0000000..5c4e1eb --- /dev/null +++ b/utils_ctboard.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ---------------------------------------------------------------------------- + * -- + * -- Project : CT Board - Cortex M4 + * -- Description : Utilities for ct board. + * -- + * -- $Id: utils_ctboard.c 2160 2015-06-08 12:28:00Z feur $ + * ------------------------------------------------------------------------- */ + +#include +#include "utils_ctboard.h" + +/* ---------------------------------------------------------------------------- + * -- Functions + * ---------------------------------------------------------------------------- + */ + +/* + * See header file + */ +uint8_t read_byte(uint32_t address) +{ + uint8_t *pointer; + pointer = (uint8_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint16_t read_halfword(uint32_t address) +{ + uint16_t *pointer; + pointer = (uint16_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint32_t read_word(uint32_t address) +{ + uint32_t *pointer; + pointer = (uint32_t *)address; + return *pointer; +} + +/* + * See header file + */ +uint64_t read_doubleword(uint32_t address) +{ + uint64_t *pointer; + pointer = (uint64_t *)address; + return *pointer; +} + + +/* + * See header file + */ +void write_byte(uint32_t address, uint8_t data) +{ + uint8_t *pointer; + pointer = (uint8_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_halfword(uint32_t address, uint16_t data) +{ + uint16_t *pointer; + pointer = (uint16_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_word(uint32_t address, uint32_t data) +{ + uint32_t *pointer; + pointer = (uint32_t *)address; + *pointer = data; +} + +/* + * See header file + */ +void write_doubleword(uint32_t address, uint64_t data) +{ + uint64_t *pointer; + pointer = (uint64_t *)address; + *pointer = data; +} diff --git a/utils_ctboard.h b/utils_ctboard.h new file mode 100644 index 0000000..b946a56 --- /dev/null +++ b/utils_ctboard.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * -- _____ ______ _____ - + * -- |_ _| | ____|/ ____| - + * -- | | _ __ | |__ | (___ Institute of Embedded Systems - + * -- | | | '_ \| __| \___ \ Zurich University of - + * -- _| |_| | | | |____ ____) | Applied Sciences - + * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - + * ---------------------------------------------------------------------------- + * -- + * -- Module : ctboard_utils + * -- Description : Interface for module. + * -- + * -- $Id: utils_ctboard.h 1122 2015-01-06 13:57:04Z feur $ + * ------------------------------------------------------------------------- */ +#ifndef _UTILS_CTBOARD +#define _UTILS_CTBOARD + +#include + +/* ---------------------------------------------------------------------------- + * -- Function prototypes + * ---------------------------------------------------------------------------- + */ + +/* + * Functions to read either a byte, halfword, word or + * doubleword from an arbitrary address. + * @param address: address to read from (32 bit) + * @retval data @ address + */ +uint8_t read_byte(uint32_t address); +uint16_t read_halfword(uint32_t address); +uint32_t read_word(uint32_t address); +uint64_t read_doubleword(uint32_t address); + + +/* + * Functions to write either a byte, halfword, word or + * doubleword to an arbitrary address. + * @param address: address to write to (32 bit) + * data: data to write @ address + */ +void write_byte(uint32_t address, uint8_t data); +void write_halfword(uint32_t address, uint16_t data); +void write_word(uint32_t address, uint32_t data); +void write_doubleword(uint32_t address, uint64_t data); + +/* ---------------------------------------------------------------------------- + * -- Header file end + * ---------------------------------------------------------------------------- + */ +#endif