ADC_IRQHandler ⇒ ADC_IRQHandler
+
+
+
+Function Pointers
+
+ - ADC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- BusFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN1_TX_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN2_RX0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN2_RX1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN2_SCE_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CAN2_TX_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- CRYP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DCMI_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA1_Stream7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2D_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DMA2_Stream7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- DebugMon_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- ETH_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- ETH_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI0_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI15_10_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- EXTI9_5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- FLASH_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- FMC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- FPU_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- HASH_RNG_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- HardFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C1_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C1_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C2_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C2_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C3_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- I2C3_EV_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- LTDC_ER_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- LTDC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- MemManage_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- NMI_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_FS_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_FS_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_HS_EP1_IN_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_HS_EP1_OUT_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_HS_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- OTG_HS_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- PVD_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- PendSV_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- RCC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- RTC_Alarm_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- RTC_WKUP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- Reset_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SAI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SDIO_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SPI6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SVC_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- SysTick_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TAMP_STAMP_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM1_BRK_TIM9_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM1_CC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM1_TRG_COM_TIM11_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM1_UP_TIM10_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM6_DAC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM8_BRK_TIM12_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM8_CC_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM8_TRG_COM_TIM14_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- TIM8_UP_TIM13_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- UART4_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- UART5_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- UART7_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- UART8_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- USART1_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- USART2_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- USART3_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- USART6_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- UsageFault_Handler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- WWDG_IRQHandler from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
+
- __main from datainit_ctboard.o(.text) referenced from startup_ctboard.o(.text)
+
- __system from system_ctboard.o(.text) referenced from startup_ctboard.o(.text)
+
- main from add64.o(MyCode) referenced from datainit_ctboard.o(.text)
+
+
+
+Global Symbols
+
+__main (Thumb, 74 bytes, Stack size 0 bytes, datainit_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(.text)
+
+Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_ctboard.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+CRYP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2D_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+HASH_RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+LTDC_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+LTDC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+SPI6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+UART7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+UART8_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
+
[Address Reference Count : 1]
- startup_ctboard.o(RESET)
+
+__system (Thumb, 8 bytes, Stack size 8 bytes, system_ctboard.o(.text))
+
[Stack]
- Max Depth = 132
- Call Chain = __system ⇒ system_enter_run ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output
+
+
[Calls]
+
[Address Reference Count : 1]- startup_ctboard.o(.text)
+
+system_enter_run (Thumb, 280 bytes, Stack size 48 bytes, system_ctboard.o(.text))
+
[Stack]
- Max Depth = 124
- Call Chain = system_enter_run ⇒ hal_gpio_init_alternate ⇒ hal_gpio_init_output
+
+
[Calls]- >> hal_fmc_init_sram
+
- >> hal_gpio_init_alternate
+
- >> hal_rcc_setup_clock
+
- >> hal_pwr_set_overdrive
+
- >> hal_rcc_setup_pll
+
- >> hal_rcc_set_osc
+
- >> hal_rcc_reset
+
+
[Called By]
+
+system_enter_sleep (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
+
+
system_enter_stop (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
+
+
system_enter_standby (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
+
+
hal_fmc_reset (Thumb, 60 bytes, Stack size 0 bytes, hal_fmc.o(.text), UNUSED)
+
+
hal_fmc_init_sram (Thumb, 264 bytes, Stack size 36 bytes, hal_fmc.o(.text))
+
[Stack]
- Max Depth = 36
- Call Chain = hal_fmc_init_sram
+
+
[Called By]
+
+hal_gpio_reset (Thumb, 68 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_init_input (Thumb, 156 bytes, Stack size 32 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_init_analog (Thumb, 240 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_init_output (Thumb, 276 bytes, Stack size 36 bytes, hal_gpio.o(.text))
+
[Stack]
- Max Depth = 36
- Call Chain = hal_gpio_init_output
+
+
[Called By]- >> hal_gpio_init_alternate
+
+
+hal_gpio_init_alternate (Thumb, 262 bytes, Stack size 40 bytes, hal_gpio.o(.text))
+
[Stack]
- Max Depth = 76
- Call Chain = hal_gpio_init_alternate ⇒ hal_gpio_init_output
+
+
[Calls]- >> hal_gpio_init_output
+
+
[Called By]
+
+hal_gpio_input_read (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_output_read (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_output_write (Thumb, 20 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_bit_set (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_bit_reset (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_bit_toggle (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_irq_set (Thumb, 292 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_irq_status (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_gpio_irq_clear (Thumb, 12 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
+
+
hal_pwr_reset (Thumb, 16 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_pwr_set_backup_domain (Thumb, 56 bytes, Stack size 16 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_pwr_set_backup_access (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_pwr_set_wakeup_pin (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_pwr_set_flash_powerdown (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_pwr_set_overdrive (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text))
+
[Called By]
+
+hal_pwr_set_underdrive (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
+
+
hal_rcc_reset (Thumb, 104 bytes, Stack size 16 bytes, hal_rcc.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = hal_rcc_reset
+
+
[Called By]
+
+hal_rcc_set_peripheral (Thumb, 228 bytes, Stack size 8 bytes, hal_rcc.o(.text), UNUSED)
+
+
hal_rcc_set_osc (Thumb, 108 bytes, Stack size 16 bytes, hal_rcc.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = hal_rcc_set_osc
+
+
[Called By]
+
+hal_rcc_setup_pll (Thumb, 220 bytes, Stack size 24 bytes, hal_rcc.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = hal_rcc_setup_pll
+
+
[Called By]
+
+hal_rcc_setup_clock (Thumb, 80 bytes, Stack size 16 bytes, hal_rcc.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = hal_rcc_setup_clock
+
+
[Called By]
+
+main (Thumb, 64 bytes, Stack size 0 bytes, add64.o(MyCode))
+
[Address Reference Count : 1]
- datainit_ctboard.o(.text)
+
+
+Local Symbols
+
+
+Undefined Global Symbols
+
diff --git a/add64/build/add64.lnp b/add64/build/add64.lnp
new file mode 100644
index 0000000..abf2c92
--- /dev/null
+++ b/add64/build/add64.lnp
@@ -0,0 +1,13 @@
+--cpu Cortex-M0
+".\build\add64.o"
+".\build\datainit_ctboard.o"
+".\build\startup_ctboard.o"
+".\build\system_ctboard.o"
+".\build\hal_fmc.o"
+".\build\hal_gpio.o"
+".\build\hal_pwr.o"
+".\build\hal_rcc.o"
+--strict --scatter ".\build\add64.sct"
+--diag_suppress 6314 --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\build\add64.map" -o .\build\add64.axf
\ No newline at end of file
diff --git a/add64/build/add64.lst b/add64/build/add64.lst
new file mode 100644
index 0000000..39b0217
--- /dev/null
+++ b/add64/build/add64.lst
@@ -0,0 +1,329 @@
+
+
+
+ARM Macro Assembler Page 1
+
+
+ 1 00000000 ; ------------------------------------------------------
+ ------------
+ 2 00000000 ; -- _____ ______ _____
+ -
+ 3 00000000 ; -- |_ _| | ____|/ ____|
+ -
+ 4 00000000 ; -- | | _ __ | |__ | (___ Institute of Embedded
+ Systems -
+ 5 00000000 ; -- | | | '_ \| __| \___ \ Zurich University of
+ -
+ 6 00000000 ; -- _| |_| | | | |____ ____) | Applied Sciences
+ -
+ 7 00000000 ; -- |_____|_| |_|______|_____/ 8401 Winterthur, Switz
+ erland -
+ 8 00000000 ; ------------------------------------------------------
+ ------------
+ 9 00000000 ; --
+ 10 00000000 ; -- add64.s
+ 11 00000000 ; --
+ 12 00000000 ; -- CT1 P05 64 Bit Addition
+ 13 00000000 ; --
+ 14 00000000 ; -- $Id: add64.s 3712 2016-10-20 08:44:57Z kesr $
+ 15 00000000 ; ------------------------------------------------------
+ ------------
+ 16 00000000 ;Directives
+ 17 00000000 PRESERVE8
+ 18 00000000 THUMB
+ 19 00000000
+ 20 00000000 ; ------------------------------------------------------
+ ------------
+ 21 00000000 ; -- Symbolic Literals
+ 22 00000000 ; ------------------------------------------------------
+ ------------
+ 23 00000000 60000200
+ ADDR_DIP_SWITCH_31_0
+ EQU 0x60000200
+ 24 00000000 60000210
+ ADDR_BUTTONS
+ EQU 0x60000210
+ 25 00000000 60000340
+ ADDR_LCD_RED
+ EQU 0x60000340
+ 26 00000000 60000342
+ ADDR_LCD_GREEN
+ EQU 0x60000342
+ 27 00000000 60000344
+ ADDR_LCD_BLUE
+ EQU 0x60000344
+ 28 00000000 60000330
+ ADDR_LCD_BIN
+ EQU 0x60000330
+ 29 00000000 00000001
+ MASK_KEY_T0
+ EQU 0x00000001
+ 30 00000000 0000FFFF
+ BACKLIGHT_FULL
+ EQU 0xffff
+ 31 00000000
+ 32 00000000 ; ------------------------------------------------------
+
+
+
+ARM Macro Assembler Page 2
+
+
+ ------------
+ 33 00000000 ; -- myCode
+ 34 00000000 ; ------------------------------------------------------
+ ------------
+ 35 00000000 AREA MyCode, CODE, READONLY
+ 36 00000000
+ 37 00000000 main PROC
+ 38 00000000 EXPORT main
+ 39 00000000
+ 40 00000000 user_prog
+ 41 00000000 4F0F LDR R7, =ADDR_LCD_BLUE ; load base
+ address of pwm blue
+
+ 42 00000002 4E10 LDR R6, =BACKLIGHT_FULL ; backlight
+ full blue
+ 43 00000004 803E STRH R6, [R7] ; write pwm registe
+ r
+ 44 00000006
+ 45 00000006 4810 LDR R0, =0 ; lower 32 bits of
+ total sum
+ 46 00000008 490F LDR R1, =0 ; higher 32 bits of
+ total sum
+ 47 0000000A endless
+ 48 0000000A F000 F80D BL waitForKey ; wait for key T0 t
+ o be pressed
+ 49 0000000E
+ 50 0000000E ; STUDENTS: To be programmed
+ 51 0000000E
+ 52 0000000E 4A0F LDR R2, =ADDR_DIP_SWITCH_31_0
+ 53 00000010 6812 LDR R2, [R2] ; Read Values of Di
+ p Switches
+ 54 00000012
+ 55 00000012
+ 56 00000012 1880 ADDS R0, R0, R2 ; Add Value of Dip
+ Siwtches to R0
+ 57 00000014
+ 58 00000014 F3EF 8400 MRS R4, APSR ; Read Flags to R4
+ 59 00000018 0F64 LSRS R4, R4, #29 ; Move Flags 24 Bit
+ right
+ 60 0000001A 4D0D LDR R5, =MASK_KEY_T0
+ 61 0000001C 402C ANDS R4, R4, R5 ; Mask only carry F
+ lag
+ 62 0000001E 1909 ADDS R1, R1, R4 ; Add Carry Flag to
+ R1
+ 63 00000020
+ 64 00000020
+ 65 00000020 4B0C LDR R3, =ADDR_LCD_BIN
+ 66 00000022 6018 STR R0, [R3, #0] ; write lower 32 B
+ its to LCD Display
+ 67 00000024 6059 STR R1, [R3, #4] ; write higher 32
+ Bits to LCD Display
+
+ 68 00000026
+ 69 00000026
+ 70 00000026
+ 71 00000026
+ 72 00000026 ; END: To be programmed
+ 73 00000026 E7F0 B endless
+ 74 00000028 ALIGN
+
+
+
+ARM Macro Assembler Page 3
+
+
+ 75 00000028
+ 76 00000028
+ 77 00000028 ;----------------------------------------------------
+ 78 00000028 ; Subroutines
+ 79 00000028 ;----------------------------------------------------
+ 80 00000028
+ 81 00000028 ; wait for key to be pressed and released
+ 82 00000028 waitForKey
+ 83 00000028 B407 PUSH {R0, R1, R2}
+ 84 0000002A 490B LDR R1, =ADDR_BUTTONS ; laod base a
+ ddress of keys
+ 85 0000002C 4A08 LDR R2, =MASK_KEY_T0
+ ; load key mask T0
+ 86 0000002E
+ 87 0000002E waitForPress
+ 88 0000002E 7808 LDRB R0, [R1] ; load key values
+ 89 00000030 4210 TST R0, R2 ; check, if key T0
+ is pressed
+ 90 00000032 D0FC BEQ waitForPress
+ 91 00000034
+ 92 00000034 waitForRelease
+ 93 00000034 7808 LDRB R0, [R1] ; load key values
+ 94 00000036 4210 TST R0, R2 ; check, if key T0
+ is released
+ 95 00000038 D1FC BNE waitForRelease
+ 96 0000003A
+ 97 0000003A BC07 POP {R0, R1, R2}
+ 98 0000003C 4770 BX LR
+ 99 0000003E 00 00 ALIGN
+ 100 00000040
+ 101 00000040 ; ------------------------------------------------------
+ ------------
+ 102 00000040 ; End of code
+ 103 00000040 ; ------------------------------------------------------
+ ------------
+ 104 00000040 ENDP
+ 105 00000040 END
+ 60000344
+ 0000FFFF
+ 00000000
+ 60000200
+ 00000001
+ 60000330
+ 60000210
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
+ild\add64.d -o.\build\add64.o -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\
+Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Loca
+l\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData
+\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --predefine="__EVAL SETA
+1" --predefine="__UVISION_VERSION SETA 537" --predefine="_RTE_ SETA 1" --predef
+ine="_RTE_ SETA 1" --list=.\build\add64.lst app\add64.s
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+MyCode 00000000
+
+Symbol: MyCode
+ Definitions
+ At line 35 in file app\add64.s
+ Uses
+ None
+Comment: MyCode unused
+endless 0000000A
+
+Symbol: endless
+ Definitions
+ At line 47 in file app\add64.s
+ Uses
+ At line 73 in file app\add64.s
+Comment: endless used once
+main 00000000
+
+Symbol: main
+ Definitions
+ At line 37 in file app\add64.s
+ Uses
+ At line 38 in file app\add64.s
+Comment: main used once
+user_prog 00000000
+
+Symbol: user_prog
+ Definitions
+ At line 40 in file app\add64.s
+ Uses
+ None
+Comment: user_prog unused
+waitForKey 00000028
+
+Symbol: waitForKey
+ Definitions
+ At line 82 in file app\add64.s
+ Uses
+ At line 48 in file app\add64.s
+Comment: waitForKey used once
+waitForPress 0000002E
+
+Symbol: waitForPress
+ Definitions
+ At line 87 in file app\add64.s
+ Uses
+ At line 90 in file app\add64.s
+Comment: waitForPress used once
+waitForRelease 00000034
+
+Symbol: waitForRelease
+ Definitions
+ At line 92 in file app\add64.s
+ Uses
+ At line 95 in file app\add64.s
+Comment: waitForRelease used once
+7 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+ADDR_BUTTONS 60000210
+
+Symbol: ADDR_BUTTONS
+ Definitions
+ At line 24 in file app\add64.s
+ Uses
+ At line 84 in file app\add64.s
+Comment: ADDR_BUTTONS used once
+ADDR_DIP_SWITCH_31_0 60000200
+
+Symbol: ADDR_DIP_SWITCH_31_0
+ Definitions
+ At line 23 in file app\add64.s
+ Uses
+ At line 52 in file app\add64.s
+Comment: ADDR_DIP_SWITCH_31_0 used once
+ADDR_LCD_BIN 60000330
+
+Symbol: ADDR_LCD_BIN
+ Definitions
+ At line 28 in file app\add64.s
+ Uses
+ At line 65 in file app\add64.s
+Comment: ADDR_LCD_BIN used once
+ADDR_LCD_BLUE 60000344
+
+Symbol: ADDR_LCD_BLUE
+ Definitions
+ At line 27 in file app\add64.s
+ Uses
+ At line 41 in file app\add64.s
+Comment: ADDR_LCD_BLUE used once
+ADDR_LCD_GREEN 60000342
+
+Symbol: ADDR_LCD_GREEN
+ Definitions
+ At line 26 in file app\add64.s
+ Uses
+ None
+Comment: ADDR_LCD_GREEN unused
+ADDR_LCD_RED 60000340
+
+Symbol: ADDR_LCD_RED
+ Definitions
+ At line 25 in file app\add64.s
+ Uses
+ None
+Comment: ADDR_LCD_RED unused
+BACKLIGHT_FULL 0000FFFF
+
+Symbol: BACKLIGHT_FULL
+ Definitions
+ At line 30 in file app\add64.s
+ Uses
+ At line 42 in file app\add64.s
+Comment: BACKLIGHT_FULL used once
+MASK_KEY_T0 00000001
+
+Symbol: MASK_KEY_T0
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+Absolute symbols
+
+ Definitions
+ At line 29 in file app\add64.s
+ Uses
+ At line 60 in file app\add64.s
+ At line 85 in file app\add64.s
+
+8 symbols
+350 symbols in table
diff --git a/add64/build/add64.map b/add64/build/add64.map
new file mode 100644
index 0000000..6e632bb
--- /dev/null
+++ b/add64/build/add64.map
@@ -0,0 +1,363 @@
+Component: Arm Compiler for Embedded 6.18 Tool: armlink [5e4cc100]
+
+==============================================================================
+
+Section Cross References
+
+ datainit_ctboard.o(.text) refers (Weak) to startup_ctboard.o(STACK) for Stack_Mem
+ datainit_ctboard.o(.text) refers to add64.o(MyCode) for main
+ startup_ctboard.o(RESET) refers to startup_ctboard.o(STACK) for __initial_sp
+ startup_ctboard.o(RESET) refers to startup_ctboard.o(.text) for Reset_Handler
+ startup_ctboard.o(.text) refers to system_ctboard.o(.text) for __system
+ startup_ctboard.o(.text) refers to datainit_ctboard.o(.text) for __main
+ system_ctboard.o(.text) refers to hal_rcc.o(.text) for hal_rcc_reset
+ system_ctboard.o(.text) refers to hal_pwr.o(.text) for hal_pwr_set_overdrive
+ system_ctboard.o(.text) refers to hal_gpio.o(.text) for hal_gpio_init_alternate
+ system_ctboard.o(.text) refers to hal_fmc.o(.text) for hal_fmc_init_sram
+ system_ctboard.o(.ARM.exidx) refers to system_ctboard.o(.text) for [Anonymous Symbol]
+ hal_fmc.o(.ARM.exidx) refers to hal_fmc.o(.text) for [Anonymous Symbol]
+ hal_gpio.o(.ARM.exidx) refers to hal_gpio.o(.text) for [Anonymous Symbol]
+ hal_pwr.o(.ARM.exidx) refers to hal_pwr.o(.text) for [Anonymous Symbol]
+ hal_rcc.o(.ARM.exidx) refers to hal_rcc.o(.text) for [Anonymous Symbol]
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+ Removing startup_ctboard.o(HEAP), (2048 bytes).
+ Removing system_ctboard.o(.ARM.exidx), (40 bytes).
+ Removing hal_fmc.o(.ARM.exidx), (16 bytes).
+ Removing hal_gpio.o(.ARM.exidx), (112 bytes).
+ Removing hal_pwr.o(.ARM.exidx), (56 bytes).
+ Removing hal_rcc.o(.ARM.exidx), (40 bytes).
+
+6 unused section(s) (total 2312 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+ Local Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s 0x00000000 Number 0 datainit_ctboard.o ABSOLUTE
+ RTE/Device/CT_Board_HS14_M0/startup_ctboard.s 0x00000000 Number 0 startup_ctboard.o ABSOLUTE
+ app\add64.s 0x00000000 Number 0 add64.o ABSOLUTE
+ hal_fmc.c 0x00000000 Number 0 hal_fmc.o ABSOLUTE
+ hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE
+ hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE
+ hal_rcc.c 0x00000000 Number 0 hal_rcc.o ABSOLUTE
+ system_ctboard.c 0x00000000 Number 0 system_ctboard.o ABSOLUTE
+ RESET 0x08000000 Section 428 startup_ctboard.o(RESET)
+ .text 0x080001ac Section 124 datainit_ctboard.o(.text)
+ .text 0x08000228 Section 36 startup_ctboard.o(.text)
+ [Anonymous Symbol] 0x0800024c Section 0 system_ctboard.o(.text)
+ __arm_cp.1_0 0x0800036c Number 4 system_ctboard.o(.text)
+ __arm_cp.1_1 0x08000370 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_2 0x08000374 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_3 0x08000378 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_4 0x0800037c Number 4 system_ctboard.o(.text)
+ __arm_cp.1_5 0x08000380 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_6 0x08000384 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_7 0x08000388 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_8 0x0800038c Number 4 system_ctboard.o(.text)
+ __arm_cp.1_9 0x08000390 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_10 0x08000394 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_11 0x08000398 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_12 0x0800039c Number 4 system_ctboard.o(.text)
+ __arm_cp.1_13 0x080003a0 Number 4 system_ctboard.o(.text)
+ __arm_cp.1_14 0x080003a4 Number 4 system_ctboard.o(.text)
+ [Anonymous Symbol] 0x080003b0 Section 0 hal_fmc.o(.text)
+ __arm_cp.0_0 0x080003ec Number 4 hal_fmc.o(.text)
+ __arm_cp.0_1 0x080003f0 Number 4 hal_fmc.o(.text)
+ __arm_cp.0_2 0x080003f4 Number 4 hal_fmc.o(.text)
+ __arm_cp.1_0 0x08000500 Number 4 hal_fmc.o(.text)
+ [Anonymous Symbol] 0x08000504 Section 0 hal_gpio.o(.text)
+ __arm_cp.0_0 0x08000548 Number 4 hal_gpio.o(.text)
+ __arm_cp.0_1 0x0800054c Number 4 hal_gpio.o(.text)
+ __arm_cp.1_0 0x080005ec Number 4 hal_gpio.o(.text)
+ __arm_cp.1_1 0x080005f0 Number 4 hal_gpio.o(.text)
+ __arm_cp.2_0 0x080006e4 Number 4 hal_gpio.o(.text)
+ __arm_cp.2_1 0x080006e8 Number 4 hal_gpio.o(.text)
+ __arm_cp.3_0 0x08000800 Number 4 hal_gpio.o(.text)
+ __arm_cp.3_1 0x08000804 Number 4 hal_gpio.o(.text)
+ __arm_cp.7_0 0x08000930 Number 4 hal_gpio.o(.text)
+ __arm_cp.7_1 0x08000934 Number 4 hal_gpio.o(.text)
+ __arm_cp.8_0 0x08000950 Number 4 hal_gpio.o(.text)
+ __arm_cp.8_1 0x08000954 Number 4 hal_gpio.o(.text)
+ __arm_cp.9_0 0x08000974 Number 4 hal_gpio.o(.text)
+ __arm_cp.9_1 0x08000978 Number 4 hal_gpio.o(.text)
+ __arm_cp.10_0 0x08000998 Number 4 hal_gpio.o(.text)
+ __arm_cp.10_1 0x0800099c Number 4 hal_gpio.o(.text)
+ __arm_cp.11_0 0x08000ac4 Number 4 hal_gpio.o(.text)
+ __arm_cp.11_1 0x08000ac8 Number 4 hal_gpio.o(.text)
+ __arm_cp.11_2 0x08000acc Number 4 hal_gpio.o(.text)
+ __arm_cp.11_3 0x08000ad0 Number 4 hal_gpio.o(.text)
+ __arm_cp.11_4 0x08000ad4 Number 4 hal_gpio.o(.text)
+ __arm_cp.11_5 0x08000ad8 Number 4 hal_gpio.o(.text)
+ __arm_cp.12_0 0x08000af4 Number 4 hal_gpio.o(.text)
+ __arm_cp.13_0 0x08000b04 Number 4 hal_gpio.o(.text)
+ [Anonymous Symbol] 0x08000b08 Section 0 hal_pwr.o(.text)
+ __arm_cp.0_0 0x08000b18 Number 4 hal_pwr.o(.text)
+ __arm_cp.1_0 0x08000b54 Number 4 hal_pwr.o(.text)
+ __arm_cp.2_0 0x08000b70 Number 4 hal_pwr.o(.text)
+ __arm_cp.3_0 0x08000b8c Number 4 hal_pwr.o(.text)
+ __arm_cp.4_0 0x08000ba8 Number 4 hal_pwr.o(.text)
+ [Anonymous Symbol] 0x08000bb4 Section 0 hal_rcc.o(.text)
+ __arm_cp.0_0 0x08000c1c Number 4 hal_rcc.o(.text)
+ __arm_cp.0_1 0x08000c20 Number 4 hal_rcc.o(.text)
+ __arm_cp.0_2 0x08000c24 Number 4 hal_rcc.o(.text)
+ __arm_cp.0_3 0x08000c28 Number 4 hal_rcc.o(.text)
+ __arm_cp.0_4 0x08000c2c Number 4 hal_rcc.o(.text)
+ __arm_cp.0_5 0x08000c30 Number 4 hal_rcc.o(.text)
+ __arm_cp.0_6 0x08000c34 Number 4 hal_rcc.o(.text)
+ __arm_cp.0_7 0x08000c38 Number 4 hal_rcc.o(.text)
+ __arm_cp.1_0 0x08000d20 Number 4 hal_rcc.o(.text)
+ __arm_cp.2_0 0x08000d90 Number 4 hal_rcc.o(.text)
+ __arm_cp.2_1 0x08000d94 Number 4 hal_rcc.o(.text)
+ __arm_cp.3_0 0x08000e74 Number 4 hal_rcc.o(.text)
+ __arm_cp.3_1 0x08000e78 Number 4 hal_rcc.o(.text)
+ __arm_cp.3_2 0x08000e7c Number 4 hal_rcc.o(.text)
+ __arm_cp.3_3 0x08000e80 Number 4 hal_rcc.o(.text)
+ __arm_cp.3_4 0x08000e84 Number 4 hal_rcc.o(.text)
+ __arm_cp.3_5 0x08000e88 Number 4 hal_rcc.o(.text)
+ __arm_cp.4_0 0x08000edc Number 4 hal_rcc.o(.text)
+ __arm_cp.4_1 0x08000ee0 Number 4 hal_rcc.o(.text)
+ MyCode 0x08000ee4 Section 92 add64.o(MyCode)
+ STACK 0x20000000 Section 8192 startup_ctboard.o(STACK)
+ __initial_sp 0x20002000 Data 0 startup_ctboard.o(STACK)
+
+ Global Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$WCHAR32$ENUMINT$~SHL$OTIME$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
+ Image$$RO$$Limit - Undefined Weak Reference
+ Image$$RW$$Base - Undefined Weak Reference
+ Image$$ZI$$Base - Undefined Weak Reference
+ Image$$ZI$$Limit - Undefined Weak Reference
+ __Vectors_Size 0x000001ac Number 0 startup_ctboard.o ABSOLUTE
+ Stack_Size 0x00002000 Number 0 startup_ctboard.o ABSOLUTE
+ __Vectors 0x08000000 Data 4 startup_ctboard.o(RESET)
+ __Vectors_End 0x080001ac Data 0 startup_ctboard.o(RESET)
+ __main 0x080001ad Thumb Code 74 datainit_ctboard.o(.text)
+ Reset_Handler 0x08000229 Thumb Code 8 startup_ctboard.o(.text)
+ NMI_Handler 0x08000231 Thumb Code 2 startup_ctboard.o(.text)
+ HardFault_Handler 0x08000233 Thumb Code 2 startup_ctboard.o(.text)
+ MemManage_Handler 0x08000235 Thumb Code 2 startup_ctboard.o(.text)
+ BusFault_Handler 0x08000237 Thumb Code 2 startup_ctboard.o(.text)
+ UsageFault_Handler 0x08000239 Thumb Code 2 startup_ctboard.o(.text)
+ SVC_Handler 0x0800023b Thumb Code 2 startup_ctboard.o(.text)
+ DebugMon_Handler 0x0800023d Thumb Code 2 startup_ctboard.o(.text)
+ PendSV_Handler 0x0800023f Thumb Code 2 startup_ctboard.o(.text)
+ SysTick_Handler 0x08000241 Thumb Code 2 startup_ctboard.o(.text)
+ ADC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN1_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN1_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN1_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN1_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN2_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN2_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN2_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CAN2_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ CRYP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DCMI_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA1_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2D_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ DMA2_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ ETH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ ETH_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI15_10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ EXTI9_5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ FLASH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ FMC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ FPU_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ HASH_RNG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C1_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C1_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C2_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C2_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C3_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ I2C3_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ LTDC_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ LTDC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_FS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_FS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_HS_EP1_IN_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_HS_EP1_OUT_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_HS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ OTG_HS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ PVD_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ RCC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ RTC_Alarm_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ RTC_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SAI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SDIO_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ SPI6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TAMP_STAMP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM1_BRK_TIM9_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM1_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM1_TRG_COM_TIM11_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM1_UP_TIM10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM6_DAC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM8_BRK_TIM12_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM8_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM8_TRG_COM_TIM14_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ TIM8_UP_TIM13_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ UART4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ UART5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ UART7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ UART8_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ USART1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ USART2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ USART3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ USART6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ WWDG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
+ __system 0x0800024d Thumb Code 8 system_ctboard.o(.text)
+ system_enter_run 0x08000255 Thumb Code 280 system_ctboard.o(.text)
+ system_enter_sleep 0x080003a9 Thumb Code 2 system_ctboard.o(.text)
+ system_enter_stop 0x080003ab Thumb Code 2 system_ctboard.o(.text)
+ system_enter_standby 0x080003ad Thumb Code 2 system_ctboard.o(.text)
+ hal_fmc_reset 0x080003b1 Thumb Code 60 hal_fmc.o(.text)
+ hal_fmc_init_sram 0x080003f9 Thumb Code 264 hal_fmc.o(.text)
+ hal_gpio_reset 0x08000505 Thumb Code 68 hal_gpio.o(.text)
+ hal_gpio_init_input 0x08000551 Thumb Code 156 hal_gpio.o(.text)
+ hal_gpio_init_analog 0x080005f5 Thumb Code 240 hal_gpio.o(.text)
+ hal_gpio_init_output 0x080006ed Thumb Code 276 hal_gpio.o(.text)
+ hal_gpio_init_alternate 0x08000809 Thumb Code 262 hal_gpio.o(.text)
+ hal_gpio_input_read 0x0800090f Thumb Code 6 hal_gpio.o(.text)
+ hal_gpio_output_read 0x08000915 Thumb Code 6 hal_gpio.o(.text)
+ hal_gpio_output_write 0x0800091d Thumb Code 20 hal_gpio.o(.text)
+ hal_gpio_bit_set 0x08000939 Thumb Code 24 hal_gpio.o(.text)
+ hal_gpio_bit_reset 0x08000959 Thumb Code 28 hal_gpio.o(.text)
+ hal_gpio_bit_toggle 0x0800097d Thumb Code 28 hal_gpio.o(.text)
+ hal_gpio_irq_set 0x080009a1 Thumb Code 292 hal_gpio.o(.text)
+ hal_gpio_irq_status 0x08000add Thumb Code 24 hal_gpio.o(.text)
+ hal_gpio_irq_clear 0x08000af9 Thumb Code 12 hal_gpio.o(.text)
+ hal_pwr_reset 0x08000b09 Thumb Code 16 hal_pwr.o(.text)
+ hal_pwr_set_backup_domain 0x08000b1d Thumb Code 56 hal_pwr.o(.text)
+ hal_pwr_set_backup_access 0x08000b59 Thumb Code 24 hal_pwr.o(.text)
+ hal_pwr_set_wakeup_pin 0x08000b75 Thumb Code 24 hal_pwr.o(.text)
+ hal_pwr_set_flash_powerdown 0x08000b91 Thumb Code 24 hal_pwr.o(.text)
+ hal_pwr_set_overdrive 0x08000bad Thumb Code 4 hal_pwr.o(.text)
+ hal_pwr_set_underdrive 0x08000bb1 Thumb Code 4 hal_pwr.o(.text)
+ hal_rcc_reset 0x08000bb5 Thumb Code 104 hal_rcc.o(.text)
+ hal_rcc_set_peripheral 0x08000c3d Thumb Code 228 hal_rcc.o(.text)
+ hal_rcc_set_osc 0x08000d25 Thumb Code 108 hal_rcc.o(.text)
+ hal_rcc_setup_pll 0x08000d99 Thumb Code 220 hal_rcc.o(.text)
+ hal_rcc_setup_clock 0x08000e8d Thumb Code 80 hal_rcc.o(.text)
+ main 0x08000ee5 Thumb Code 64 add64.o(MyCode)
+ Image$$ER_IROM1$$Limit 0x08000f40 Number 0 anon$$obj.o ABSOLUTE
+ Image$$RW_IRAM1$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE
+ Image$$RW_IRAM1$$ZI$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE
+ Stack_Mem 0x20000000 Data 8192 startup_ctboard.o(STACK)
+ Image$$RW_IRAM1$$ZI$$Limit 0x20002000 Number 0 anon$$obj.o ABSOLUTE
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+ Image Entry point : 0x08000229
+
+ Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000f40, Max: 0x00200000, ABSOLUTE)
+
+ Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000f40, Max: 0x00200000, ABSOLUTE)
+
+ Exec Addr Load Addr Size Type Attr Idx E Section Name Object
+
+ 0x08000000 0x08000000 0x000001ac Data RO 13 RESET startup_ctboard.o
+ 0x080001ac 0x080001ac 0x0000007c Code RO 7 .text datainit_ctboard.o
+ 0x08000228 0x08000228 0x00000024 Code RO 14 * .text startup_ctboard.o
+ 0x0800024c 0x0800024c 0x00000162 Code RO 18 .text system_ctboard.o
+ 0x080003ae 0x080003ae 0x00000002 PAD
+ 0x080003b0 0x080003b0 0x00000154 Code RO 26 .text hal_fmc.o
+ 0x08000504 0x08000504 0x00000604 Code RO 34 .text hal_gpio.o
+ 0x08000b08 0x08000b08 0x000000ac Code RO 42 .text hal_pwr.o
+ 0x08000bb4 0x08000bb4 0x00000330 Code RO 50 .text hal_rcc.o
+ 0x08000ee4 0x08000ee4 0x0000005c Code RO 1 MyCode add64.o
+
+
+ Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000f40, Size: 0x00002000, Max: 0x00030000, ABSOLUTE)
+
+ Exec Addr Load Addr Size Type Attr Idx E Section Name Object
+
+ 0x20000000 - 0x00002000 Zero RW 11 STACK startup_ctboard.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Object Name
+
+ 92 30 0 0 0 364 add64.o
+ 124 50 0 0 0 412 datainit_ctboard.o
+ 340 16 0 0 0 3820 hal_fmc.o
+ 1540 96 0 0 0 11984 hal_gpio.o
+ 172 20 0 0 0 2115 hal_pwr.o
+ 816 168 0 0 0 5343 hal_rcc.o
+ 36 8 428 0 8192 812 startup_ctboard.o
+ 354 60 0 0 0 6754 system_ctboard.o
+
+ ----------------------------------------------------------------------
+ 3476 448 428 0 8192 31604 Object Totals
+ 0 0 0 0 0 0 (incl. Generated)
+ 2 0 0 0 0 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+ 0 0 0 0 0 0 Library Totals
+ 0 0 0 0 0 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+
+==============================================================================
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug
+
+ 3476 448 428 0 8192 31420 Grand Totals
+ 3476 448 428 0 8192 31420 ELF Image Totals
+ 3476 448 428 0 0 0 ROM Totals
+
+==============================================================================
+
+ Total RO Size (Code + RO Data) 3904 ( 3.81kB)
+ Total RW Size (RW Data + ZI Data) 8192 ( 8.00kB)
+ Total ROM Size (Code + RO Data + RW Data) 3904 ( 3.81kB)
+
+==============================================================================
+
diff --git a/add64/build/add64.o b/add64/build/add64.o
new file mode 100644
index 0000000..f7f130f
Binary files /dev/null and b/add64/build/add64.o differ
diff --git a/add64/build/add64.sct b/add64/build/add64.sct
new file mode 100644
index 0000000..5394321
--- /dev/null
+++ b/add64/build/add64.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00030000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/add64/build/add64_Target 1.dep b/add64/build/add64_Target 1.dep
new file mode 100644
index 0000000..8f54792
--- /dev/null
+++ b/add64/build/add64_Target 1.dep
@@ -0,0 +1,36 @@
+Dependencies for Project 'add64', Target 'Target 1': (DO NOT MODIFY !)
+CompilerVersion: 6180000::V6.18::ARMCLANG
+F (.\app\add64.s)(0x635260B0)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g
-I.\RTE\_Target_1
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include
--pd "__UVISION_VERSION SETA 537"
--pd "_RTE_ SETA 1"
--pd "_RTE_ SETA 1"
--list .\build\add64.lst
--xref -o .\build\add64.o
--depend .\build\add64.d)
+F (RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g
-I.\RTE\_Target_1
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include
--pd "__UVISION_VERSION SETA 537"
--pd "_RTE_ SETA 1"
--pd "_RTE_ SETA 1"
--list .\build\datainit_ctboard.lst
--xref -o .\build\datainit_ctboard.o
--depend .\build\datainit_ctboard.d)
+F (RTE/Device/CT_Board_HS14_M0/startup_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g
-I.\RTE\_Target_1
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0
-IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include
--pd "__UVISION_VERSION SETA 537"
--pd "_RTE_ SETA 1"
--pd "_RTE_ SETA 1"
--list .\build\startup_ctboard.lst
--xref -o .\build\startup_ctboard.o
--depend .\build\startup_ctboard.d)
+F (RTE/Device/CT_Board_HS14_M0/system_ctboard.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c
-fno-rtti -funsigned-char
-D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier
-I./RTE/_Target_1
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
-D__UVISION_VERSION="537" -D_RTE_ -D_RTE_
-o ./build/system_ctboard.o -MD)
+I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h)(0x5C6AA868)
+F (RTE/HAL/CT_Board_HS14_M0/hal_fmc.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c
-fno-rtti -funsigned-char
-D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier
-I./RTE/_Target_1
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
-D__UVISION_VERSION="537" -D_RTE_ -D_RTE_
-o ./build/hal_fmc.o -MD)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
+I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
+F (RTE/HAL/CT_Board_HS14_M0/hal_gpio.c)(0x5C5ACEB0)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c
-fno-rtti -funsigned-char
-D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier
-I./RTE/_Target_1
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
-D__UVISION_VERSION="537" -D_RTE_ -D_RTE_
-o ./build/hal_gpio.o -MD)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
+I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
+F (RTE/HAL/CT_Board_HS14_M0/hal_pwr.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c
-fno-rtti -funsigned-char
-D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier
-I./RTE/_Target_1
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
-D__UVISION_VERSION="537" -D_RTE_ -D_RTE_
-o ./build/hal_pwr.o -MD)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
+I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
+F (RTE/HAL/CT_Board_HS14_M0/hal_rcc.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c
-fno-rtti -funsigned-char
-D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier
-I./RTE/_Target_1
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
-IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
-D__UVISION_VERSION="537" -D_RTE_ -D_RTE_
-o ./build/hal_rcc.o -MD)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
+I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
+I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
diff --git a/add64/build/datainit_ctboard.d b/add64/build/datainit_ctboard.d
new file mode 100644
index 0000000..9edaee9
--- /dev/null
+++ b/add64/build/datainit_ctboard.d
@@ -0,0 +1 @@
+.\build\datainit_ctboard.o: RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
diff --git a/add64/build/datainit_ctboard.lst b/add64/build/datainit_ctboard.lst
new file mode 100644
index 0000000..653a32c
--- /dev/null
+++ b/add64/build/datainit_ctboard.lst
@@ -0,0 +1,372 @@
+
+
+
+ARM Macro Assembler Page 1
+
+
+ 1 00000000 ;* -----------------------------------------------------
+ -------------
+ 2 00000000 ;* -- _____ ______ _____
+ -
+ 3 00000000 ;* -- |_ _| | ____|/ ____|
+ -
+ 4 00000000 ;* -- | | _ __ | |__ | (___ Institute of Embedded
+ Systems -
+ 5 00000000 ;* -- | | | '_ \| __| \___ \ Zurich University of
+ -
+ 6 00000000 ;* -- _| |_| | | | |____ ____) | Applied Sciences
+ -
+ 7 00000000 ;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Swit
+ zerland -
+ 8 00000000 ;* -----------------------------------------------------
+ -------------
+ 9 00000000 ;* --
+ 10 00000000 ;* -- Project : CT Board - Cortex M4
+ 11 00000000 ;* -- Description : Data Segment initialisation.
+ 12 00000000 ;* --
+ 13 00000000 ;* -- $Id$
+ 14 00000000 ;* -----------------------------------------------------
+ -------------
+ 15 00000000
+ 16 00000000
+ 17 00000000 ; ------------------------------------------------------
+ -------------
+ 18 00000000 ; -- __Main
+ 19 00000000 ; ------------------------------------------------------
+ -------------
+ 20 00000000
+ 21 00000000 AREA |.text|, CODE, READONLY
+ 22 00000000
+ 23 00000000 IMPORT main
+ 24 00000000
+ 25 00000000 EXPORT __main
+ 26 00000000
+ 27 00000000 __main PROC
+ 28 00000000
+ 29 00000000 ; initialize RW and ZI data - this includes heap and sta
+ ck for the -ro=... -rw=... -entry=... linking cmd args..
+ .
+ 30 00000000 IMPORT |Image$$RO$$Limit| [WEAK]
+ 31 00000000 IMPORT |Image$$RW$$Base| [WEAK]
+ 32 00000000 IMPORT |Image$$ZI$$Base| [WEAK]
+ 33 00000000 IMPORT |Image$$ZI$$Limit| [WEAK]
+ 34 00000000 ; ...or from auto generated scatter file. Needs linker o
+ ption: --diag_suppress 6314
+ 35 00000000 IMPORT |Image$$ER_IROM1$$Limit| [W
+EAK]
+ 36 00000000 IMPORT |Image$$RW_IRAM1$$Base| [W
+EAK]
+ 37 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Base| [W
+EAK]
+ 38 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [W
+EAK]
+ 39 00000000 ; import stack parameter
+ 40 00000000 IMPORT Stack_Size [WEAK]
+ 41 00000000 IMPORT Stack_Mem [WEAK]
+
+
+
+ARM Macro Assembler Page 2
+
+
+ 42 00000000
+ 43 00000000 ; switch between command line generated regions and auto
+ scatter file generated regions
+ 44 00000000 4912 LDR R1, =|Image$$RO$$Limit|
+ 45 00000002 2900 CMP R1,#0
+ 46 00000004 D004 BEQ ScatterFileSymbols
+ 47 00000006 CommandLineSymbols
+ 48 00000006 4A12 LDR R2, =|Image$$RW$$Base| ; start
+ of the RW data in R
+ AM
+ 49 00000008 4B12 LDR R3, =|Image$$ZI$$Base| ; end of
+ the RW data in RAM
+
+ 50 0000000A 461D MOV R5, R3 ; start of zero ini
+ tialized data
+ 51 0000000C 4E12 LDR R6, =|Image$$ZI$$Limit| ; end o
+ f zero initialized
+ data
+ 52 0000000E E009 B CondRWLoop
+ 53 00000010 ScatterFileSymbols
+ 54 00000010 4912 LDR R1, =|Image$$ER_IROM1$$Limit| ;
+ start of flashed i
+ nitial RW data
+ 55 00000012 4A13 LDR R2, =|Image$$RW_IRAM1$$Base| ;
+ start of the RW dat
+ a in RAM
+ 56 00000014 4B13 LDR R3, =|Image$$RW_IRAM1$$ZI$$Base
+|
+ ; end of the RW dat
+ a in RAM
+ 57 00000016 461D MOV R5, R3 ; start of zero ini
+ tialized data
+ 58 00000018 4E13 LDR R6, =|Image$$RW_IRAM1$$ZI$$Limi
+t|
+ ; end of zero initi
+ alized data
+ 59 0000001A E003 B CondRWLoop
+ 60 0000001C
+ 61 0000001C ; init non-zero data
+ 62 0000001C 680C LoopRWCopy
+ LDR R4, [R1]
+ 63 0000001E 6014 STR R4, [R2]
+ 64 00000020 1D09 ADDS R1, R1, #4
+ 65 00000022 1D12 ADDS R2, R2, #4
+ 66 00000024 429A CondRWLoop
+ CMP R2, R3
+ 67 00000026 D1F9 BNE LoopRWCopy
+ 68 00000028
+ 69 00000028 ; init zero-initialized data
+ 70 00000028 462A MOV R2, R5
+ 71 0000002A 4633 MOV R3, R6
+ 72 0000002C 2400 MOVS R4, #0
+ 73 0000002E E001 B CondZILoop
+ 74 00000030 6014 LoopZICopy
+ STR R4, [R2]
+ 75 00000032 1D12 ADDS R2, R2, #4
+ 76 00000034 429A CondZILoop
+ CMP R2, R3
+ 77 00000036 D1FB BNE LoopZICopy
+
+
+
+ARM Macro Assembler Page 3
+
+
+ 78 00000038
+ 79 00000038 ; fingerprint stack section
+ 80 00000038 480C LDR R0, =Stack_Mem
+ 81 0000003A 490D LDR R1, =Stack_Size
+ 82 0000003C 4A0D LDR R2, =0xEFBEADDE ; stack fingerp
+ rint (little endian
+ !)
+ 83 0000003E 6002 LoopStack
+ STR R2, [R0]
+ 84 00000040 1D00 ADDS R0, R0, #4
+ 85 00000042 3904 SUBS R1, #4
+ 86 00000044 D1FB BNE LoopStack
+ 87 00000046
+ 88 00000046 ; go to the user main function
+ 89 00000046 480C LDR R0, =main
+ 90 00000048 4700 BX R0
+ 91 0000004A ENDP
+ 92 0000004A
+ 93 0000004A
+ 94 0000004A ; ------------------------------------------------------
+ -------------
+ 95 0000004A ; -- End of file
+ 96 0000004A ; ------------------------------------------------------
+ -------------
+ 97 0000004A
+ 98 0000004A 00 00 ALIGN
+ 99 0000004C
+ 100 0000004C END
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ 00000000
+ EFBEADDE
+ 00000000
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
+ild\datainit_ctboard.d -o.\build\datainit_ctboard.o -I.\RTE\_Target_1 -IC:\User
+s\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Us
+ers\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -I
+C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --p
+redefine="__EVAL SETA 1" --predefine="__UVISION_VERSION SETA 537" --predefine="
+_RTE_ SETA 1" --predefine="_RTE_ SETA 1" --list=.\build\datainit_ctboard.lst RT
+E/Device/CT_Board_HS14_M0/datainit_ctboard.s
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+ Definitions
+ At line 21 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ None
+Comment: .text unused
+CommandLineSymbols 00000006
+
+Symbol: CommandLineSymbols
+ Definitions
+ At line 47 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ None
+Comment: CommandLineSymbols unused
+CondRWLoop 00000024
+
+Symbol: CondRWLoop
+ Definitions
+ At line 66 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 52 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ At line 59 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+
+CondZILoop 00000034
+
+Symbol: CondZILoop
+ Definitions
+ At line 76 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 73 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: CondZILoop used once
+LoopRWCopy 0000001C
+
+Symbol: LoopRWCopy
+ Definitions
+ At line 62 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 67 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: LoopRWCopy used once
+LoopStack 0000003E
+
+Symbol: LoopStack
+ Definitions
+ At line 83 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 86 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: LoopStack used once
+LoopZICopy 00000030
+
+Symbol: LoopZICopy
+ Definitions
+ At line 74 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 77 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: LoopZICopy used once
+ScatterFileSymbols 00000010
+
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: ScatterFileSymbols
+ Definitions
+ At line 53 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 46 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: ScatterFileSymbols used once
+__main 00000000
+
+Symbol: __main
+ Definitions
+ At line 27 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 25 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: __main used once
+9 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+External symbols
+
+Image$$ER_IROM1$$Limit 00000000
+
+Symbol: Image$$ER_IROM1$$Limit
+ Definitions
+ At line 35 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 54 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$ER_IROM1$$Limit used once
+Image$$RO$$Limit 00000000
+
+Symbol: Image$$RO$$Limit
+ Definitions
+ At line 30 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 44 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$RO$$Limit used once
+Image$$RW$$Base 00000000
+
+Symbol: Image$$RW$$Base
+ Definitions
+ At line 31 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 48 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$RW$$Base used once
+Image$$RW_IRAM1$$Base 00000000
+
+Symbol: Image$$RW_IRAM1$$Base
+ Definitions
+ At line 36 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 55 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$RW_IRAM1$$Base used once
+Image$$RW_IRAM1$$ZI$$Base 00000000
+
+Symbol: Image$$RW_IRAM1$$ZI$$Base
+ Definitions
+ At line 37 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 56 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$RW_IRAM1$$ZI$$Base used once
+Image$$RW_IRAM1$$ZI$$Limit 00000000
+
+Symbol: Image$$RW_IRAM1$$ZI$$Limit
+ Definitions
+ At line 38 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 58 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$RW_IRAM1$$ZI$$Limit used once
+Image$$ZI$$Base 00000000
+
+Symbol: Image$$ZI$$Base
+ Definitions
+ At line 32 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 49 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$ZI$$Base used once
+Image$$ZI$$Limit 00000000
+
+Symbol: Image$$ZI$$Limit
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+External symbols
+
+ Definitions
+ At line 33 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 51 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Image$$ZI$$Limit used once
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+ Definitions
+ At line 41 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 80 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Stack_Mem used once
+Stack_Size 00000000
+
+Symbol: Stack_Size
+ Definitions
+ At line 40 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 81 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: Stack_Size used once
+main 00000000
+
+Symbol: main
+ Definitions
+ At line 23 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+ Uses
+ At line 89 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
+Comment: main used once
+11 symbols
+355 symbols in table
diff --git a/add64/build/datainit_ctboard.o b/add64/build/datainit_ctboard.o
new file mode 100644
index 0000000..0499f00
Binary files /dev/null and b/add64/build/datainit_ctboard.o differ
diff --git a/add64/build/hal_fmc.d b/add64/build/hal_fmc.d
new file mode 100644
index 0000000..7361834
--- /dev/null
+++ b/add64/build/hal_fmc.d
@@ -0,0 +1,5 @@
+./build/hal_fmc.o: RTE\HAL\CT_Board_HS14_M0\hal_fmc.c \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
+ C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h
diff --git a/add64/build/hal_fmc.o b/add64/build/hal_fmc.o
new file mode 100644
index 0000000..ef3a281
Binary files /dev/null and b/add64/build/hal_fmc.o differ
diff --git a/add64/build/hal_gpio.d b/add64/build/hal_gpio.d
new file mode 100644
index 0000000..48c4242
--- /dev/null
+++ b/add64/build/hal_gpio.d
@@ -0,0 +1,5 @@
+./build/hal_gpio.o: RTE\HAL\CT_Board_HS14_M0\hal_gpio.c \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
+ C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h
diff --git a/add64/build/hal_gpio.o b/add64/build/hal_gpio.o
new file mode 100644
index 0000000..d46eedd
Binary files /dev/null and b/add64/build/hal_gpio.o differ
diff --git a/add64/build/hal_pwr.d b/add64/build/hal_pwr.d
new file mode 100644
index 0000000..5a8be71
--- /dev/null
+++ b/add64/build/hal_pwr.d
@@ -0,0 +1,5 @@
+./build/hal_pwr.o: RTE\HAL\CT_Board_HS14_M0\hal_pwr.c \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
+ C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h
diff --git a/add64/build/hal_pwr.o b/add64/build/hal_pwr.o
new file mode 100644
index 0000000..fe00d2e
Binary files /dev/null and b/add64/build/hal_pwr.o differ
diff --git a/add64/build/hal_rcc.d b/add64/build/hal_rcc.d
new file mode 100644
index 0000000..184a1d5
--- /dev/null
+++ b/add64/build/hal_rcc.d
@@ -0,0 +1,5 @@
+./build/hal_rcc.o: RTE\HAL\CT_Board_HS14_M0\hal_rcc.c \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
+ C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h
diff --git a/add64/build/hal_rcc.o b/add64/build/hal_rcc.o
new file mode 100644
index 0000000..46aa4e2
Binary files /dev/null and b/add64/build/hal_rcc.o differ
diff --git a/add64/build/startup_ctboard.d b/add64/build/startup_ctboard.d
new file mode 100644
index 0000000..8fab56b
--- /dev/null
+++ b/add64/build/startup_ctboard.d
@@ -0,0 +1 @@
+.\build\startup_ctboard.o: RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
diff --git a/add64/build/startup_ctboard.lst b/add64/build/startup_ctboard.lst
new file mode 100644
index 0000000..7757b9f
--- /dev/null
+++ b/add64/build/startup_ctboard.lst
@@ -0,0 +1,2074 @@
+
+
+
+ARM Macro Assembler Page 1
+
+
+ 1 00000000 ;******************** (C) COPYRIGHT 2013 STMicroelectron
+ ics ********************
+ 2 00000000 ;* File Name : startup_stm32f429_439xx.s
+ 3 00000000 ;* Author : MCD Application Team
+ 4 00000000 ;* Version : V1.3.0
+ 5 00000000 ;* Date : 08-November-2013
+ 6 00000000 ;* Description : STM32F429xx/439xx devices vector
+ table for MDK-ARM toolchain.
+ 7 00000000 ;* This module performs:
+ 8 00000000 ;* - Set the initial SP
+ 9 00000000 ;* - Set the initial PC == Reset_Ha
+ ndler
+ 10 00000000 ;* - Set the vector table entries w
+ ith the exceptions ISR address
+ 11 00000000 ;* - Configure the system clock and
+ the external SRAM/SDRAM mounted
+ 12 00000000 ;* on STM324x9I-EVAL boards to be
+ used as data memory
+ 13 00000000 ;* (optional, to be enabled by us
+ er)
+ 14 00000000 ;* - Branches to __main in the C li
+ brary (which eventually
+ 15 00000000 ;* calls main()).
+ 16 00000000 ;* After Reset the CortexM4 process
+ or is in Thread mode,
+ 17 00000000 ;* priority is Privileged, and the
+ Stack is set to Main.
+ 18 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
+ 19 00000000 ;*******************************************************
+ ************************
+ 20 00000000 ;
+ 21 00000000 ; Licensed under MCD-ST Liberty SW License Agreement V2,
+ (the "License");
+ 22 00000000 ; You may not use this file except in compliance with th
+ e License.
+ 23 00000000 ; You may obtain a copy of the License at:
+ 24 00000000 ;
+ 25 00000000 ; http://www.st.com/software_license_agreement_li
+ berty_v2
+ 26 00000000 ;
+ 27 00000000 ; Unless required by applicable law or agreed to in writ
+ ing, software
+ 28 00000000 ; distributed under the License is distributed on an "AS
+ IS" BASIS,
+ 29 00000000 ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either e
+ xpress or implied.
+ 30 00000000 ; See the License for the specific language governing pe
+ rmissions and
+ 31 00000000 ; limitations under the License.
+ 32 00000000 ;
+ 33 00000000 ;*******************************************************
+ ************************
+ 34 00000000
+ 35 00000000 ; Amount of memory (in bytes) allocated for Stack
+ 36 00000000 ; Tailor this value to your application needs
+ 37 00000000 ; Stack Configuration
+ 38 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ 39 00000000 ;
+ 40 00000000
+
+
+
+ARM Macro Assembler Page 2
+
+
+ 41 00000000 00002000
+ Stack_Size
+ EQU 0x00002000
+ 42 00000000
+ 43 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
+=3
+ 44 00000000 EXPORT Stack_Size
+ 45 00000000 EXPORT Stack_Mem
+ 46 00000000
+ 47 00000000 Stack_Mem
+ SPACE Stack_Size
+ 48 00002000 __initial_sp
+ 49 00002000
+ 50 00002000
+ 51 00002000 ; Heap Configuration
+ 52 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ 53 00002000 ;
+ 54 00002000
+ 55 00002000 00000800
+ Heap_Size
+ EQU 0x00000800
+ 56 00002000
+ 57 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN=
+3
+ 58 00000000 __heap_base
+ 59 00000000 Heap_Mem
+ SPACE Heap_Size
+ 60 00000800 __heap_limit
+ 61 00000800
+ 62 00000800 PRESERVE8
+ 63 00000800 THUMB
+ 64 00000800
+ 65 00000800
+ 66 00000800 ; Vector Table Mapped to Address 0 at Reset
+ 67 00000800 AREA RESET, DATA, READONLY
+ 68 00000000 EXPORT __Vectors
+ 69 00000000 EXPORT __Vectors_End
+ 70 00000000 EXPORT __Vectors_Size
+ 71 00000000
+ 72 00000000
+ 73 00000000 00000000
+ __Vectors
+ DCD __initial_sp ; Top of Stack
+ 74 00000004 00000000 DCD Reset_Handler ; Reset Handler
+ 75 00000008 00000000 DCD NMI_Handler ; NMI Handler
+ 76 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
+ Handler
+ 77 00000010 00000000 DCD MemManage_Handler
+ ; MPU Fault Handler
+
+ 78 00000014 00000000 DCD BusFault_Handler
+ ; Bus Fault Handler
+
+ 79 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
+ t Handler
+ 80 0000001C 00000000 DCD 0 ; Reserved
+ 81 00000020 00000000 DCD 0 ; Reserved
+ 82 00000024 00000000 DCD 0 ; Reserved
+ 83 00000028 00000000 DCD 0 ; Reserved
+
+
+
+ARM Macro Assembler Page 3
+
+
+ 84 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
+ 85 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
+ r Handler
+ 86 00000034 00000000 DCD 0 ; Reserved
+ 87 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
+
+ 88 0000003C 00000000 DCD SysTick_Handler
+ ; SysTick Handler
+ 89 00000040
+ 90 00000040 ; External Interrupts
+ 91 00000040 00000000 DCD WWDG_IRQHandler ; Window WatchD
+ og
+
+
+ 92 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
+ TI Line detection
+
+
+ 93 00000048 00000000 DCD TAMP_STAMP_IRQHandler ; Tamper
+ and TimeStamps thro
+ ugh the EXTI line
+
+ 94 0000004C 00000000 DCD RTC_WKUP_IRQHandler ; RTC Wakeu
+ p through the EXTI
+ line
+
+ 95 00000050 00000000 DCD FLASH_IRQHandler ; FLASH
+
+
+ 96 00000054 00000000 DCD RCC_IRQHandler ; RCC
+
+
+ 97 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line0
+
+
+
+ 98 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line1
+
+
+
+ 99 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line2
+
+
+
+ 100 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line3
+
+
+
+ 101 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line4
+
+
+
+ 102 0000006C 00000000 DCD DMA1_Stream0_IRQHandler ; DMA1
+ Stream 0
+
+
+ 103 00000070 00000000 DCD DMA1_Stream1_IRQHandler ; DMA1
+ Stream 1
+
+
+
+
+ARM Macro Assembler Page 4
+
+
+
+ 104 00000074 00000000 DCD DMA1_Stream2_IRQHandler ; DMA1
+ Stream 2
+
+
+ 105 00000078 00000000 DCD DMA1_Stream3_IRQHandler ; DMA1
+ Stream 3
+
+
+ 106 0000007C 00000000 DCD DMA1_Stream4_IRQHandler ; DMA1
+ Stream 4
+
+
+ 107 00000080 00000000 DCD DMA1_Stream5_IRQHandler ; DMA1
+ Stream 5
+
+
+ 108 00000084 00000000 DCD DMA1_Stream6_IRQHandler ; DMA1
+ Stream 6
+
+
+ 109 00000088 00000000 DCD ADC_IRQHandler ; ADC1, ADC2 and
+ ADC3s
+
+ 110 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX
+
+
+
+ 111 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+
+
+
+ 112 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+
+
+
+ 113 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+
+
+
+ 114 0000009C 00000000 DCD EXTI9_5_IRQHandler ; External L
+ ine[9:5]s
+
+
+ 115 000000A0 00000000 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1
+ Break and TIM9
+
+ 116 000000A4 00000000 DCD TIM1_UP_TIM10_IRQHandler ; TIM1
+ Update and TIM10
+
+ 117 000000A8 00000000 DCD TIM1_TRG_COM_TIM11_IRQHandler ;
+ TIM1 Trigger and C
+ ommutation and TIM1
+ 1
+ 118 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
+ re Compare
+
+
+ 119 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
+
+
+
+ARM Macro Assembler Page 5
+
+
+
+
+ 120 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
+
+
+ 121 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
+
+
+ 122 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
+
+
+
+ 123 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
+
+
+
+ 124 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
+
+
+
+ 125 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
+
+
+
+ 126 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
+
+
+ 127 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
+
+
+ 128 000000D4 00000000 DCD USART1_IRQHandler ; USART1
+
+
+ 129 000000D8 00000000 DCD USART2_IRQHandler ; USART2
+
+
+ 130 000000DC 00000000 DCD USART3_IRQHandler ; USART3
+
+
+ 131 000000E0 00000000 DCD EXTI15_10_IRQHandler ; External
+ Line[15:10]s
+
+
+ 132 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar
+ m (A and B) through
+ EXTI Line
+
+ 133 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT
+ G FS Wakeup through
+ EXTI line
+
+ 134 000000EC 00000000 DCD TIM8_BRK_TIM12_IRQHandler ; TIM
+ 8 Break and TIM12
+
+ 135 000000F0 00000000 DCD TIM8_UP_TIM13_IRQHandler ; TIM8
+ Update and TIM13
+
+ 136 000000F4 00000000 DCD TIM8_TRG_COM_TIM14_IRQHandler ;
+ TIM8 Trigger and C
+
+
+
+ARM Macro Assembler Page 6
+
+
+ ommutation and TIM1
+ 4
+ 137 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu
+ re Compare
+
+
+ 138 000000FC 00000000 DCD DMA1_Stream7_IRQHandler ; DMA1
+ Stream7
+
+
+ 139 00000100 00000000 DCD FMC_IRQHandler ; FMC
+
+
+ 140 00000104 00000000 DCD SDIO_IRQHandler ; SDIO
+
+
+ 141 00000108 00000000 DCD TIM5_IRQHandler ; TIM5
+
+
+ 142 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3
+
+
+ 143 00000110 00000000 DCD UART4_IRQHandler ; UART4
+
+
+ 144 00000114 00000000 DCD UART5_IRQHandler ; UART5
+
+
+ 145 00000118 00000000 DCD TIM6_DAC_IRQHandler ; TIM6 and
+ DAC1&2 underrun err
+ ors
+
+ 146 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7
+
+ 147 00000120 00000000 DCD DMA2_Stream0_IRQHandler ; DMA2
+ Stream 0
+
+
+ 148 00000124 00000000 DCD DMA2_Stream1_IRQHandler ; DMA2
+ Stream 1
+
+
+ 149 00000128 00000000 DCD DMA2_Stream2_IRQHandler ; DMA2
+ Stream 2
+
+
+ 150 0000012C 00000000 DCD DMA2_Stream3_IRQHandler ; DMA2
+ Stream 3
+
+
+ 151 00000130 00000000 DCD DMA2_Stream4_IRQHandler ; DMA2
+ Stream 4
+
+
+ 152 00000134 00000000 DCD ETH_IRQHandler ; Ethernet
+
+
+ 153 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet
+ Wakeup through EXTI
+
+
+
+ARM Macro Assembler Page 7
+
+
+ line
+
+ 154 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX
+
+
+
+ 155 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+
+
+
+ 156 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+
+
+
+ 157 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+
+
+
+ 158 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS
+
+
+ 159 00000150 00000000 DCD DMA2_Stream5_IRQHandler ; DMA2
+ Stream 5
+
+
+ 160 00000154 00000000 DCD DMA2_Stream6_IRQHandler ; DMA2
+ Stream 6
+
+
+ 161 00000158 00000000 DCD DMA2_Stream7_IRQHandler ; DMA2
+ Stream 7
+
+
+ 162 0000015C 00000000 DCD USART6_IRQHandler ; USART6
+
+
+
+ 163 00000160 00000000 DCD I2C3_EV_IRQHandler ; I2C3 event
+
+
+
+ 164 00000164 00000000 DCD I2C3_ER_IRQHandler ; I2C3 error
+
+
+
+ 165 00000168 00000000 DCD OTG_HS_EP1_OUT_IRQHandler ; USB
+ OTG HS End Point 1
+ Out
+
+ 166 0000016C 00000000 DCD OTG_HS_EP1_IN_IRQHandler ; USB
+ OTG HS End Point 1
+ In
+
+ 167 00000170 00000000 DCD OTG_HS_WKUP_IRQHandler ; USB OT
+ G HS Wakeup through
+ EXTI
+
+ 168 00000174 00000000 DCD OTG_HS_IRQHandler ; USB OTG HS
+
+
+
+
+ARM Macro Assembler Page 8
+
+
+
+ 169 00000178 00000000 DCD DCMI_IRQHandler ; DCMI
+
+
+ 170 0000017C 00000000 DCD CRYP_IRQHandler ; CRYP crypto
+
+
+ 171 00000180 00000000 DCD HASH_RNG_IRQHandler
+ ; Hash and Rng
+ 172 00000184 00000000 DCD FPU_IRQHandler ; FPU
+ 173 00000188 00000000 DCD UART7_IRQHandler ; UART7
+ 174 0000018C 00000000 DCD UART8_IRQHandler ; UART8
+ 175 00000190 00000000 DCD SPI4_IRQHandler ; SPI4
+ 176 00000194 00000000 DCD SPI5_IRQHandler ; SPI5
+ 177 00000198 00000000 DCD SPI6_IRQHandler ; SPI6
+ 178 0000019C 00000000 DCD SAI1_IRQHandler ; SAI1
+ 179 000001A0 00000000 DCD LTDC_IRQHandler ; LTDC
+ 180 000001A4 00000000 DCD LTDC_ER_IRQHandler ; LTDC error
+
+ 181 000001A8 00000000 DCD DMA2D_IRQHandler ; DMA2D
+ 182 000001AC
+ 183 000001AC __Vectors_End
+ 184 000001AC
+ 185 000001AC 000001AC
+ __Vectors_Size
+ EQU __Vectors_End - __Vectors
+ 186 000001AC
+ 187 000001AC AREA |.text|, CODE, READONLY
+ 188 00000000
+ 189 00000000 ; Reset handler
+ 190 00000000 Reset_Handler
+ PROC
+ 191 00000000 EXPORT Reset_Handler [WEAK
+]
+ 192 00000000 IMPORT __system
+ 193 00000000 IMPORT __main
+ 194 00000000 ENTRY
+ 195 00000000
+ 196 00000000 4806 LDR R0, =__system
+ 197 00000002 4780 BLX R0
+ 198 00000004 4806 LDR R0, =__main
+ 199 00000006 4700 BX R0
+ 200 00000008 ENDP
+ 201 00000008
+ 202 00000008 ; Dummy Exception Handlers (infinite loops which can be
+ modified)
+ 203 00000008
+ 204 00000008 NMI_Handler
+ PROC
+ 205 00000008 EXPORT NMI_Handler [WEA
+K]
+ 206 00000008 E7FE B .
+ 207 0000000A ENDP
+ 209 0000000A HardFault_Handler
+ PROC
+ 210 0000000A EXPORT HardFault_Handler [WEA
+K]
+ 211 0000000A E7FE B .
+ 212 0000000C ENDP
+
+
+
+ARM Macro Assembler Page 9
+
+
+ 214 0000000C MemManage_Handler
+ PROC
+ 215 0000000C EXPORT MemManage_Handler [WEA
+K]
+ 216 0000000C E7FE B .
+ 217 0000000E ENDP
+ 219 0000000E BusFault_Handler
+ PROC
+ 220 0000000E EXPORT BusFault_Handler [WEA
+K]
+ 221 0000000E E7FE B .
+ 222 00000010 ENDP
+ 224 00000010 UsageFault_Handler
+ PROC
+ 225 00000010 EXPORT UsageFault_Handler [WEA
+K]
+ 226 00000010 E7FE B .
+ 227 00000012 ENDP
+ 228 00000012 SVC_Handler
+ PROC
+ 229 00000012 EXPORT SVC_Handler [WEA
+K]
+ 230 00000012 E7FE B .
+ 231 00000014 ENDP
+ 233 00000014 DebugMon_Handler
+ PROC
+ 234 00000014 EXPORT DebugMon_Handler [WEA
+K]
+ 235 00000014 E7FE B .
+ 236 00000016 ENDP
+ 237 00000016 PendSV_Handler
+ PROC
+ 238 00000016 EXPORT PendSV_Handler [WEA
+K]
+ 239 00000016 E7FE B .
+ 240 00000018 ENDP
+ 241 00000018 SysTick_Handler
+ PROC
+ 242 00000018 EXPORT SysTick_Handler [WEA
+K]
+ 243 00000018 E7FE B .
+ 244 0000001A ENDP
+ 245 0000001A
+ 246 0000001A Default_Handler
+ PROC
+ 247 0000001A
+ 248 0000001A EXPORT WWDG_IRQHandler
+ [WEAK]
+ 249 0000001A EXPORT PVD_IRQHandler
+ [WEAK]
+ 250 0000001A EXPORT TAMP_STAMP_IRQHandler
+ [WEAK]
+ 251 0000001A EXPORT RTC_WKUP_IRQHandler
+ [WEAK]
+ 252 0000001A EXPORT FLASH_IRQHandler
+ [WEAK]
+ 253 0000001A EXPORT RCC_IRQHandler
+ [WEAK]
+ 254 0000001A EXPORT EXTI0_IRQHandler
+
+
+
+ARM Macro Assembler Page 10
+
+
+ [WEAK]
+ 255 0000001A EXPORT EXTI1_IRQHandler
+ [WEAK]
+ 256 0000001A EXPORT EXTI2_IRQHandler
+ [WEAK]
+ 257 0000001A EXPORT EXTI3_IRQHandler
+ [WEAK]
+ 258 0000001A EXPORT EXTI4_IRQHandler
+ [WEAK]
+ 259 0000001A EXPORT DMA1_Stream0_IRQHandler
+ [WEAK]
+ 260 0000001A EXPORT DMA1_Stream1_IRQHandler
+ [WEAK]
+ 261 0000001A EXPORT DMA1_Stream2_IRQHandler
+ [WEAK]
+ 262 0000001A EXPORT DMA1_Stream3_IRQHandler
+ [WEAK]
+ 263 0000001A EXPORT DMA1_Stream4_IRQHandler
+ [WEAK]
+ 264 0000001A EXPORT DMA1_Stream5_IRQHandler
+ [WEAK]
+ 265 0000001A EXPORT DMA1_Stream6_IRQHandler
+ [WEAK]
+ 266 0000001A EXPORT ADC_IRQHandler
+ [WEAK]
+ 267 0000001A EXPORT CAN1_TX_IRQHandler
+ [WEAK]
+ 268 0000001A EXPORT CAN1_RX0_IRQHandler
+ [WEAK]
+ 269 0000001A EXPORT CAN1_RX1_IRQHandler
+ [WEAK]
+ 270 0000001A EXPORT CAN1_SCE_IRQHandler
+ [WEAK]
+ 271 0000001A EXPORT EXTI9_5_IRQHandler
+ [WEAK]
+ 272 0000001A EXPORT TIM1_BRK_TIM9_IRQHandler
+ [WEAK]
+ 273 0000001A EXPORT TIM1_UP_TIM10_IRQHandler
+ [WEAK]
+ 274 0000001A EXPORT TIM1_TRG_COM_TIM11_IRQHandler
+ [WEAK]
+ 275 0000001A EXPORT TIM1_CC_IRQHandler
+ [WEAK]
+ 276 0000001A EXPORT TIM2_IRQHandler
+ [WEAK]
+ 277 0000001A EXPORT TIM3_IRQHandler
+ [WEAK]
+ 278 0000001A EXPORT TIM4_IRQHandler
+ [WEAK]
+ 279 0000001A EXPORT I2C1_EV_IRQHandler
+ [WEAK]
+ 280 0000001A EXPORT I2C1_ER_IRQHandler
+ [WEAK]
+ 281 0000001A EXPORT I2C2_EV_IRQHandler
+ [WEAK]
+ 282 0000001A EXPORT I2C2_ER_IRQHandler
+ [WEAK]
+ 283 0000001A EXPORT SPI1_IRQHandler
+ [WEAK]
+
+
+
+ARM Macro Assembler Page 11
+
+
+ 284 0000001A EXPORT SPI2_IRQHandler
+ [WEAK]
+ 285 0000001A EXPORT USART1_IRQHandler
+ [WEAK]
+ 286 0000001A EXPORT USART2_IRQHandler
+ [WEAK]
+ 287 0000001A EXPORT USART3_IRQHandler
+ [WEAK]
+ 288 0000001A EXPORT EXTI15_10_IRQHandler
+ [WEAK]
+ 289 0000001A EXPORT RTC_Alarm_IRQHandler
+ [WEAK]
+ 290 0000001A EXPORT OTG_FS_WKUP_IRQHandler
+ [WEAK]
+ 291 0000001A EXPORT TIM8_BRK_TIM12_IRQHandler
+ [WEAK]
+ 292 0000001A EXPORT TIM8_UP_TIM13_IRQHandler
+ [WEAK]
+ 293 0000001A EXPORT TIM8_TRG_COM_TIM14_IRQHandler
+ [WEAK]
+ 294 0000001A EXPORT TIM8_CC_IRQHandler
+ [WEAK]
+ 295 0000001A EXPORT DMA1_Stream7_IRQHandler
+ [WEAK]
+ 296 0000001A EXPORT FMC_IRQHandler
+ [WEAK]
+ 297 0000001A EXPORT SDIO_IRQHandler
+ [WEAK]
+ 298 0000001A EXPORT TIM5_IRQHandler
+ [WEAK]
+ 299 0000001A EXPORT SPI3_IRQHandler
+ [WEAK]
+ 300 0000001A EXPORT UART4_IRQHandler
+ [WEAK]
+ 301 0000001A EXPORT UART5_IRQHandler
+ [WEAK]
+ 302 0000001A EXPORT TIM6_DAC_IRQHandler
+ [WEAK]
+ 303 0000001A EXPORT TIM7_IRQHandler
+ [WEAK]
+ 304 0000001A EXPORT DMA2_Stream0_IRQHandler
+ [WEAK]
+ 305 0000001A EXPORT DMA2_Stream1_IRQHandler
+ [WEAK]
+ 306 0000001A EXPORT DMA2_Stream2_IRQHandler
+ [WEAK]
+ 307 0000001A EXPORT DMA2_Stream3_IRQHandler
+ [WEAK]
+ 308 0000001A EXPORT DMA2_Stream4_IRQHandler
+ [WEAK]
+ 309 0000001A EXPORT ETH_IRQHandler
+ [WEAK]
+ 310 0000001A EXPORT ETH_WKUP_IRQHandler
+ [WEAK]
+ 311 0000001A EXPORT CAN2_TX_IRQHandler
+ [WEAK]
+ 312 0000001A EXPORT CAN2_RX0_IRQHandler
+ [WEAK]
+ 313 0000001A EXPORT CAN2_RX1_IRQHandler
+
+
+
+ARM Macro Assembler Page 12
+
+
+ [WEAK]
+ 314 0000001A EXPORT CAN2_SCE_IRQHandler
+ [WEAK]
+ 315 0000001A EXPORT OTG_FS_IRQHandler
+ [WEAK]
+ 316 0000001A EXPORT DMA2_Stream5_IRQHandler
+ [WEAK]
+ 317 0000001A EXPORT DMA2_Stream6_IRQHandler
+ [WEAK]
+ 318 0000001A EXPORT DMA2_Stream7_IRQHandler
+ [WEAK]
+ 319 0000001A EXPORT USART6_IRQHandler
+ [WEAK]
+ 320 0000001A EXPORT I2C3_EV_IRQHandler
+ [WEAK]
+ 321 0000001A EXPORT I2C3_ER_IRQHandler
+ [WEAK]
+ 322 0000001A EXPORT OTG_HS_EP1_OUT_IRQHandler
+ [WEAK]
+ 323 0000001A EXPORT OTG_HS_EP1_IN_IRQHandler
+ [WEAK]
+ 324 0000001A EXPORT OTG_HS_WKUP_IRQHandler
+ [WEAK]
+ 325 0000001A EXPORT OTG_HS_IRQHandler
+ [WEAK]
+ 326 0000001A EXPORT DCMI_IRQHandler
+ [WEAK]
+ 327 0000001A EXPORT CRYP_IRQHandler
+ [WEAK]
+ 328 0000001A EXPORT HASH_RNG_IRQHandler
+ [WEAK]
+ 329 0000001A EXPORT FPU_IRQHandler
+ [WEAK]
+ 330 0000001A EXPORT UART7_IRQHandler
+ [WEAK]
+ 331 0000001A EXPORT UART8_IRQHandler
+ [WEAK]
+ 332 0000001A EXPORT SPI4_IRQHandler
+ [WEAK]
+ 333 0000001A EXPORT SPI5_IRQHandler
+ [WEAK]
+ 334 0000001A EXPORT SPI6_IRQHandler
+ [WEAK]
+ 335 0000001A EXPORT SAI1_IRQHandler
+ [WEAK]
+ 336 0000001A EXPORT LTDC_IRQHandler
+ [WEAK]
+ 337 0000001A EXPORT LTDC_ER_IRQHandler
+ [WEAK]
+ 338 0000001A EXPORT DMA2D_IRQHandler
+ [WEAK]
+ 339 0000001A
+ 340 0000001A WWDG_IRQHandler
+ 341 0000001A PVD_IRQHandler
+ 342 0000001A TAMP_STAMP_IRQHandler
+ 343 0000001A RTC_WKUP_IRQHandler
+ 344 0000001A FLASH_IRQHandler
+ 345 0000001A RCC_IRQHandler
+ 346 0000001A EXTI0_IRQHandler
+
+
+
+ARM Macro Assembler Page 13
+
+
+ 347 0000001A EXTI1_IRQHandler
+ 348 0000001A EXTI2_IRQHandler
+ 349 0000001A EXTI3_IRQHandler
+ 350 0000001A EXTI4_IRQHandler
+ 351 0000001A DMA1_Stream0_IRQHandler
+ 352 0000001A DMA1_Stream1_IRQHandler
+ 353 0000001A DMA1_Stream2_IRQHandler
+ 354 0000001A DMA1_Stream3_IRQHandler
+ 355 0000001A DMA1_Stream4_IRQHandler
+ 356 0000001A DMA1_Stream5_IRQHandler
+ 357 0000001A DMA1_Stream6_IRQHandler
+ 358 0000001A ADC_IRQHandler
+ 359 0000001A CAN1_TX_IRQHandler
+ 360 0000001A CAN1_RX0_IRQHandler
+ 361 0000001A CAN1_RX1_IRQHandler
+ 362 0000001A CAN1_SCE_IRQHandler
+ 363 0000001A EXTI9_5_IRQHandler
+ 364 0000001A TIM1_BRK_TIM9_IRQHandler
+ 365 0000001A TIM1_UP_TIM10_IRQHandler
+ 366 0000001A TIM1_TRG_COM_TIM11_IRQHandler
+ 367 0000001A TIM1_CC_IRQHandler
+ 368 0000001A TIM2_IRQHandler
+ 369 0000001A TIM3_IRQHandler
+ 370 0000001A TIM4_IRQHandler
+ 371 0000001A I2C1_EV_IRQHandler
+ 372 0000001A I2C1_ER_IRQHandler
+ 373 0000001A I2C2_EV_IRQHandler
+ 374 0000001A I2C2_ER_IRQHandler
+ 375 0000001A SPI1_IRQHandler
+ 376 0000001A SPI2_IRQHandler
+ 377 0000001A USART1_IRQHandler
+ 378 0000001A USART2_IRQHandler
+ 379 0000001A USART3_IRQHandler
+ 380 0000001A EXTI15_10_IRQHandler
+ 381 0000001A RTC_Alarm_IRQHandler
+ 382 0000001A OTG_FS_WKUP_IRQHandler
+ 383 0000001A TIM8_BRK_TIM12_IRQHandler
+ 384 0000001A TIM8_UP_TIM13_IRQHandler
+ 385 0000001A TIM8_TRG_COM_TIM14_IRQHandler
+ 386 0000001A TIM8_CC_IRQHandler
+ 387 0000001A DMA1_Stream7_IRQHandler
+ 388 0000001A FMC_IRQHandler
+ 389 0000001A SDIO_IRQHandler
+ 390 0000001A TIM5_IRQHandler
+ 391 0000001A SPI3_IRQHandler
+ 392 0000001A UART4_IRQHandler
+ 393 0000001A UART5_IRQHandler
+ 394 0000001A TIM6_DAC_IRQHandler
+ 395 0000001A TIM7_IRQHandler
+ 396 0000001A DMA2_Stream0_IRQHandler
+ 397 0000001A DMA2_Stream1_IRQHandler
+ 398 0000001A DMA2_Stream2_IRQHandler
+ 399 0000001A DMA2_Stream3_IRQHandler
+ 400 0000001A DMA2_Stream4_IRQHandler
+ 401 0000001A ETH_IRQHandler
+ 402 0000001A ETH_WKUP_IRQHandler
+ 403 0000001A CAN2_TX_IRQHandler
+ 404 0000001A CAN2_RX0_IRQHandler
+ 405 0000001A CAN2_RX1_IRQHandler
+
+
+
+ARM Macro Assembler Page 14
+
+
+ 406 0000001A CAN2_SCE_IRQHandler
+ 407 0000001A OTG_FS_IRQHandler
+ 408 0000001A DMA2_Stream5_IRQHandler
+ 409 0000001A DMA2_Stream6_IRQHandler
+ 410 0000001A DMA2_Stream7_IRQHandler
+ 411 0000001A USART6_IRQHandler
+ 412 0000001A I2C3_EV_IRQHandler
+ 413 0000001A I2C3_ER_IRQHandler
+ 414 0000001A OTG_HS_EP1_OUT_IRQHandler
+ 415 0000001A OTG_HS_EP1_IN_IRQHandler
+ 416 0000001A OTG_HS_WKUP_IRQHandler
+ 417 0000001A OTG_HS_IRQHandler
+ 418 0000001A DCMI_IRQHandler
+ 419 0000001A CRYP_IRQHandler
+ 420 0000001A HASH_RNG_IRQHandler
+ 421 0000001A FPU_IRQHandler
+ 422 0000001A UART7_IRQHandler
+ 423 0000001A UART8_IRQHandler
+ 424 0000001A SPI4_IRQHandler
+ 425 0000001A SPI5_IRQHandler
+ 426 0000001A SPI6_IRQHandler
+ 427 0000001A SAI1_IRQHandler
+ 428 0000001A LTDC_IRQHandler
+ 429 0000001A LTDC_ER_IRQHandler
+ 430 0000001A DMA2D_IRQHandler
+ 431 0000001A E7FE B .
+ 432 0000001C
+ 433 0000001C ENDP
+ 434 0000001C
+ 435 0000001C ALIGN
+ 436 0000001C
+ 437 0000001C END
+ 00000000
+ 00000000
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
+ild\startup_ctboard.d -o.\build\startup_ctboard.o -I.\RTE\_Target_1 -IC:\Users\
+roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\User
+s\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:
+\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pre
+define="__EVAL SETA 1" --predefine="__UVISION_VERSION SETA 537" --predefine="_R
+TE_ SETA 1" --predefine="_RTE_ SETA 1" --list=.\build\startup_ctboard.lst RTE/D
+evice/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+ Definitions
+ At line 43 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+ Definitions
+ At line 47 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 45 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: Stack_Mem used once
+__initial_sp 00002000
+
+Symbol: __initial_sp
+ Definitions
+ At line 48 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 73 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: __initial_sp used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+ Definitions
+ At line 57 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+ Definitions
+ At line 59 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: Heap_Mem unused
+__heap_base 00000000
+
+Symbol: __heap_base
+ Definitions
+ At line 58 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: __heap_base unused
+__heap_limit 00000800
+
+Symbol: __heap_limit
+ Definitions
+ At line 60 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: __heap_limit unused
+4 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+RESET 00000000
+
+Symbol: RESET
+ Definitions
+ At line 67 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: RESET unused
+__Vectors 00000000
+
+Symbol: __Vectors
+ Definitions
+ At line 73 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 68 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 185 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+__Vectors_End 000001AC
+
+Symbol: __Vectors_End
+ Definitions
+ At line 183 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 69 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 185 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+ Definitions
+ At line 187 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: .text unused
+ADC_IRQHandler 0000001A
+
+Symbol: ADC_IRQHandler
+ Definitions
+ At line 358 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 109 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 266 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+BusFault_Handler 0000000E
+
+Symbol: BusFault_Handler
+ Definitions
+ At line 219 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 78 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 220 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN1_RX0_IRQHandler 0000001A
+
+Symbol: CAN1_RX0_IRQHandler
+ Definitions
+ At line 360 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 111 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 268 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN1_RX1_IRQHandler 0000001A
+
+Symbol: CAN1_RX1_IRQHandler
+ Definitions
+ At line 361 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 112 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 269 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN1_SCE_IRQHandler 0000001A
+
+Symbol: CAN1_SCE_IRQHandler
+ Definitions
+ At line 362 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 113 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 270 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN1_TX_IRQHandler 0000001A
+
+Symbol: CAN1_TX_IRQHandler
+ Definitions
+ At line 359 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 110 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 267 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN2_RX0_IRQHandler 0000001A
+
+Symbol: CAN2_RX0_IRQHandler
+ Definitions
+ At line 404 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 155 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 312 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN2_RX1_IRQHandler 0000001A
+
+Symbol: CAN2_RX1_IRQHandler
+ Definitions
+ At line 405 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 156 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 313 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN2_SCE_IRQHandler 0000001A
+
+Symbol: CAN2_SCE_IRQHandler
+ Definitions
+ At line 406 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 157 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 314 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CAN2_TX_IRQHandler 0000001A
+
+Symbol: CAN2_TX_IRQHandler
+ Definitions
+ At line 403 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 154 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 311 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+CRYP_IRQHandler 0000001A
+
+Symbol: CRYP_IRQHandler
+ Definitions
+ At line 419 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 170 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 327 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DCMI_IRQHandler 0000001A
+
+Symbol: DCMI_IRQHandler
+ Definitions
+ At line 418 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 169 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 326 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream0_IRQHandler 0000001A
+
+
+
+
+ARM Macro Assembler Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: DMA1_Stream0_IRQHandler
+ Definitions
+ At line 351 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 102 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 259 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream1_IRQHandler 0000001A
+
+Symbol: DMA1_Stream1_IRQHandler
+ Definitions
+ At line 352 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 103 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 260 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream2_IRQHandler 0000001A
+
+Symbol: DMA1_Stream2_IRQHandler
+ Definitions
+ At line 353 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 104 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 261 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream3_IRQHandler 0000001A
+
+Symbol: DMA1_Stream3_IRQHandler
+ Definitions
+ At line 354 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 105 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 262 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream4_IRQHandler 0000001A
+
+Symbol: DMA1_Stream4_IRQHandler
+ Definitions
+ At line 355 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 106 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 263 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream5_IRQHandler 0000001A
+
+Symbol: DMA1_Stream5_IRQHandler
+ Definitions
+ At line 356 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 107 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 264 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream6_IRQHandler 0000001A
+
+Symbol: DMA1_Stream6_IRQHandler
+ Definitions
+ At line 357 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 108 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 4 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 265 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA1_Stream7_IRQHandler 0000001A
+
+Symbol: DMA1_Stream7_IRQHandler
+ Definitions
+ At line 387 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 138 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 295 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2D_IRQHandler 0000001A
+
+Symbol: DMA2D_IRQHandler
+ Definitions
+ At line 430 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 181 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 338 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream0_IRQHandler 0000001A
+
+Symbol: DMA2_Stream0_IRQHandler
+ Definitions
+ At line 396 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 147 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 304 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream1_IRQHandler 0000001A
+
+Symbol: DMA2_Stream1_IRQHandler
+ Definitions
+ At line 397 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 148 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 305 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream2_IRQHandler 0000001A
+
+Symbol: DMA2_Stream2_IRQHandler
+ Definitions
+ At line 398 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 149 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 306 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream3_IRQHandler 0000001A
+
+Symbol: DMA2_Stream3_IRQHandler
+ Definitions
+ At line 399 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 150 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 307 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream4_IRQHandler 0000001A
+
+Symbol: DMA2_Stream4_IRQHandler
+
+
+
+ARM Macro Assembler Page 5 Alphabetic symbol ordering
+Relocatable symbols
+
+ Definitions
+ At line 400 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 151 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 308 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream5_IRQHandler 0000001A
+
+Symbol: DMA2_Stream5_IRQHandler
+ Definitions
+ At line 408 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 159 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 316 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream6_IRQHandler 0000001A
+
+Symbol: DMA2_Stream6_IRQHandler
+ Definitions
+ At line 409 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 160 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 317 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DMA2_Stream7_IRQHandler 0000001A
+
+Symbol: DMA2_Stream7_IRQHandler
+ Definitions
+ At line 410 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 161 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 318 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+DebugMon_Handler 00000014
+
+Symbol: DebugMon_Handler
+ Definitions
+ At line 233 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 85 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 234 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+Default_Handler 0000001A
+
+Symbol: Default_Handler
+ Definitions
+ At line 246 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ None
+Comment: Default_Handler unused
+ETH_IRQHandler 0000001A
+
+Symbol: ETH_IRQHandler
+ Definitions
+ At line 401 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 152 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 309 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+
+ARM Macro Assembler Page 6 Alphabetic symbol ordering
+Relocatable symbols
+
+ETH_WKUP_IRQHandler 0000001A
+
+Symbol: ETH_WKUP_IRQHandler
+ Definitions
+ At line 402 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 153 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 310 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI0_IRQHandler 0000001A
+
+Symbol: EXTI0_IRQHandler
+ Definitions
+ At line 346 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 97 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 254 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI15_10_IRQHandler 0000001A
+
+Symbol: EXTI15_10_IRQHandler
+ Definitions
+ At line 380 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 131 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 288 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI1_IRQHandler 0000001A
+
+Symbol: EXTI1_IRQHandler
+ Definitions
+ At line 347 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 98 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 255 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI2_IRQHandler 0000001A
+
+Symbol: EXTI2_IRQHandler
+ Definitions
+ At line 348 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 99 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 256 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI3_IRQHandler 0000001A
+
+Symbol: EXTI3_IRQHandler
+ Definitions
+ At line 349 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 100 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 257 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI4_IRQHandler 0000001A
+
+Symbol: EXTI4_IRQHandler
+ Definitions
+ At line 350 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 7 Alphabetic symbol ordering
+Relocatable symbols
+
+ Uses
+ At line 101 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 258 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+EXTI9_5_IRQHandler 0000001A
+
+Symbol: EXTI9_5_IRQHandler
+ Definitions
+ At line 363 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 114 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 271 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+FLASH_IRQHandler 0000001A
+
+Symbol: FLASH_IRQHandler
+ Definitions
+ At line 344 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 95 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 252 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+FMC_IRQHandler 0000001A
+
+Symbol: FMC_IRQHandler
+ Definitions
+ At line 388 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 139 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 296 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+FPU_IRQHandler 0000001A
+
+Symbol: FPU_IRQHandler
+ Definitions
+ At line 421 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 172 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 329 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+HASH_RNG_IRQHandler 0000001A
+
+Symbol: HASH_RNG_IRQHandler
+ Definitions
+ At line 420 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 171 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 328 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+HardFault_Handler 0000000A
+
+Symbol: HardFault_Handler
+ Definitions
+ At line 209 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 76 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 210 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C1_ER_IRQHandler 0000001A
+
+
+
+ARM Macro Assembler Page 8 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: I2C1_ER_IRQHandler
+ Definitions
+ At line 372 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 123 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 280 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C1_EV_IRQHandler 0000001A
+
+Symbol: I2C1_EV_IRQHandler
+ Definitions
+ At line 371 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 122 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 279 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C2_ER_IRQHandler 0000001A
+
+Symbol: I2C2_ER_IRQHandler
+ Definitions
+ At line 374 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 125 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 282 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C2_EV_IRQHandler 0000001A
+
+Symbol: I2C2_EV_IRQHandler
+ Definitions
+ At line 373 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 124 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 281 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C3_ER_IRQHandler 0000001A
+
+Symbol: I2C3_ER_IRQHandler
+ Definitions
+ At line 413 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 164 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 321 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+I2C3_EV_IRQHandler 0000001A
+
+Symbol: I2C3_EV_IRQHandler
+ Definitions
+ At line 412 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 163 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 320 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+LTDC_ER_IRQHandler 0000001A
+
+Symbol: LTDC_ER_IRQHandler
+ Definitions
+ At line 429 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+
+
+
+ARM Macro Assembler Page 9 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 180 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 337 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+LTDC_IRQHandler 0000001A
+
+Symbol: LTDC_IRQHandler
+ Definitions
+ At line 428 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 179 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 336 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+MemManage_Handler 0000000C
+
+Symbol: MemManage_Handler
+ Definitions
+ At line 214 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 77 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 215 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+NMI_Handler 00000008
+
+Symbol: NMI_Handler
+ Definitions
+ At line 204 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 75 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 205 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_FS_IRQHandler 0000001A
+
+Symbol: OTG_FS_IRQHandler
+ Definitions
+ At line 407 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 158 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 315 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_FS_WKUP_IRQHandler 0000001A
+
+Symbol: OTG_FS_WKUP_IRQHandler
+ Definitions
+ At line 382 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 133 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 290 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_HS_EP1_IN_IRQHandler 0000001A
+
+Symbol: OTG_HS_EP1_IN_IRQHandler
+ Definitions
+ At line 415 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 166 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 323 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_HS_EP1_OUT_IRQHandler 0000001A
+
+
+
+
+ARM Macro Assembler Page 10 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: OTG_HS_EP1_OUT_IRQHandler
+ Definitions
+ At line 414 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 165 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 322 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_HS_IRQHandler 0000001A
+
+Symbol: OTG_HS_IRQHandler
+ Definitions
+ At line 417 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 168 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 325 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+OTG_HS_WKUP_IRQHandler 0000001A
+
+Symbol: OTG_HS_WKUP_IRQHandler
+ Definitions
+ At line 416 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 167 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 324 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+PVD_IRQHandler 0000001A
+
+Symbol: PVD_IRQHandler
+ Definitions
+ At line 341 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 92 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 249 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+PendSV_Handler 00000016
+
+Symbol: PendSV_Handler
+ Definitions
+ At line 237 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 87 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 238 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+RCC_IRQHandler 0000001A
+
+Symbol: RCC_IRQHandler
+ Definitions
+ At line 345 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 96 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 253 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+RTC_Alarm_IRQHandler 0000001A
+
+Symbol: RTC_Alarm_IRQHandler
+ Definitions
+ At line 381 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 132 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 11 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 289 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+RTC_WKUP_IRQHandler 0000001A
+
+Symbol: RTC_WKUP_IRQHandler
+ Definitions
+ At line 343 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 94 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 251 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+Reset_Handler 00000000
+
+Symbol: Reset_Handler
+ Definitions
+ At line 190 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 74 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 191 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SAI1_IRQHandler 0000001A
+
+Symbol: SAI1_IRQHandler
+ Definitions
+ At line 427 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 178 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 335 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SDIO_IRQHandler 0000001A
+
+Symbol: SDIO_IRQHandler
+ Definitions
+ At line 389 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 140 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 297 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI1_IRQHandler 0000001A
+
+Symbol: SPI1_IRQHandler
+ Definitions
+ At line 375 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 126 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 283 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI2_IRQHandler 0000001A
+
+Symbol: SPI2_IRQHandler
+ Definitions
+ At line 376 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 127 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 284 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI3_IRQHandler 0000001A
+
+Symbol: SPI3_IRQHandler
+
+
+
+ARM Macro Assembler Page 12 Alphabetic symbol ordering
+Relocatable symbols
+
+ Definitions
+ At line 391 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 142 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 299 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI4_IRQHandler 0000001A
+
+Symbol: SPI4_IRQHandler
+ Definitions
+ At line 424 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 175 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 332 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI5_IRQHandler 0000001A
+
+Symbol: SPI5_IRQHandler
+ Definitions
+ At line 425 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 176 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 333 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SPI6_IRQHandler 0000001A
+
+Symbol: SPI6_IRQHandler
+ Definitions
+ At line 426 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 177 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 334 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SVC_Handler 00000012
+
+Symbol: SVC_Handler
+ Definitions
+ At line 228 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 84 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 229 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+SysTick_Handler 00000018
+
+Symbol: SysTick_Handler
+ Definitions
+ At line 241 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 88 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 242 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TAMP_STAMP_IRQHandler 0000001A
+
+Symbol: TAMP_STAMP_IRQHandler
+ Definitions
+ At line 342 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 93 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 250 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 13 Alphabetic symbol ordering
+Relocatable symbols
+
+
+TIM1_BRK_TIM9_IRQHandler 0000001A
+
+Symbol: TIM1_BRK_TIM9_IRQHandler
+ Definitions
+ At line 364 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 115 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 272 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM1_CC_IRQHandler 0000001A
+
+Symbol: TIM1_CC_IRQHandler
+ Definitions
+ At line 367 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 118 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 275 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM1_TRG_COM_TIM11_IRQHandler 0000001A
+
+Symbol: TIM1_TRG_COM_TIM11_IRQHandler
+ Definitions
+ At line 366 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 117 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 274 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM1_UP_TIM10_IRQHandler 0000001A
+
+Symbol: TIM1_UP_TIM10_IRQHandler
+ Definitions
+ At line 365 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 116 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 273 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM2_IRQHandler 0000001A
+
+Symbol: TIM2_IRQHandler
+ Definitions
+ At line 368 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 119 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 276 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM3_IRQHandler 0000001A
+
+Symbol: TIM3_IRQHandler
+ Definitions
+ At line 369 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 120 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 277 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM4_IRQHandler 0000001A
+
+Symbol: TIM4_IRQHandler
+ Definitions
+
+
+
+ARM Macro Assembler Page 14 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 370 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 121 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 278 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM5_IRQHandler 0000001A
+
+Symbol: TIM5_IRQHandler
+ Definitions
+ At line 390 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 141 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 298 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM6_DAC_IRQHandler 0000001A
+
+Symbol: TIM6_DAC_IRQHandler
+ Definitions
+ At line 394 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 145 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 302 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM7_IRQHandler 0000001A
+
+Symbol: TIM7_IRQHandler
+ Definitions
+ At line 395 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 146 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 303 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM8_BRK_TIM12_IRQHandler 0000001A
+
+Symbol: TIM8_BRK_TIM12_IRQHandler
+ Definitions
+ At line 383 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 134 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 291 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM8_CC_IRQHandler 0000001A
+
+Symbol: TIM8_CC_IRQHandler
+ Definitions
+ At line 386 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 137 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 294 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+TIM8_TRG_COM_TIM14_IRQHandler 0000001A
+
+Symbol: TIM8_TRG_COM_TIM14_IRQHandler
+ Definitions
+ At line 385 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 136 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 293 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+
+ARM Macro Assembler Page 15 Alphabetic symbol ordering
+Relocatable symbols
+
+TIM8_UP_TIM13_IRQHandler 0000001A
+
+Symbol: TIM8_UP_TIM13_IRQHandler
+ Definitions
+ At line 384 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 135 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 292 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+UART4_IRQHandler 0000001A
+
+Symbol: UART4_IRQHandler
+ Definitions
+ At line 392 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 143 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 300 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+UART5_IRQHandler 0000001A
+
+Symbol: UART5_IRQHandler
+ Definitions
+ At line 393 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 144 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 301 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+UART7_IRQHandler 0000001A
+
+Symbol: UART7_IRQHandler
+ Definitions
+ At line 422 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 173 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 330 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+UART8_IRQHandler 0000001A
+
+Symbol: UART8_IRQHandler
+ Definitions
+ At line 423 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 174 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 331 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+USART1_IRQHandler 0000001A
+
+Symbol: USART1_IRQHandler
+ Definitions
+ At line 377 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 128 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 285 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+USART2_IRQHandler 0000001A
+
+Symbol: USART2_IRQHandler
+ Definitions
+ At line 378 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+
+
+ARM Macro Assembler Page 16 Alphabetic symbol ordering
+Relocatable symbols
+
+ Uses
+ At line 129 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 286 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+USART3_IRQHandler 0000001A
+
+Symbol: USART3_IRQHandler
+ Definitions
+ At line 379 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 130 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 287 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+USART6_IRQHandler 0000001A
+
+Symbol: USART6_IRQHandler
+ Definitions
+ At line 411 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 162 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 319 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+UsageFault_Handler 00000010
+
+Symbol: UsageFault_Handler
+ Definitions
+ At line 224 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 79 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 225 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+WWDG_IRQHandler 0000001A
+
+Symbol: WWDG_IRQHandler
+ Definitions
+ At line 340 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 91 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 248 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+103 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+Heap_Size 00000800
+
+Symbol: Heap_Size
+ Definitions
+ At line 55 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 59 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: Heap_Size used once
+Stack_Size 00002000
+
+Symbol: Stack_Size
+ Definitions
+ At line 41 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 44 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ At line 47 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+
+__Vectors_Size 000001AC
+
+Symbol: __Vectors_Size
+ Definitions
+ At line 185 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 70 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: __Vectors_Size used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+External symbols
+
+__main 00000000
+
+Symbol: __main
+ Definitions
+ At line 193 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 198 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: __main used once
+__system 00000000
+
+Symbol: __system
+ Definitions
+ At line 192 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+ Uses
+ At line 196 in file RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
+Comment: __system used once
+2 symbols
+453 symbols in table
diff --git a/add64/build/startup_ctboard.o b/add64/build/startup_ctboard.o
new file mode 100644
index 0000000..350fe59
Binary files /dev/null and b/add64/build/startup_ctboard.o differ
diff --git a/add64/build/system_ctboard.d b/add64/build/system_ctboard.d
new file mode 100644
index 0000000..556de8b
--- /dev/null
+++ b/add64/build/system_ctboard.d
@@ -0,0 +1,11 @@
+./build/system_ctboard.o: RTE\Device\CT_Board_HS14_M0\system_ctboard.c \
+ C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
+ C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h
diff --git a/add64/build/system_ctboard.o b/add64/build/system_ctboard.o
new file mode 100644
index 0000000..6a8bf9c
Binary files /dev/null and b/add64/build/system_ctboard.o differ
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 b/arith_operations/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1
new file mode 100644
index 0000000..d891d1a
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1
@@ -0,0 +1,100 @@
+;* ------------------------------------------------------------------
+;* -- _____ ______ _____ -
+;* -- |_ _| | ____|/ ____| -
+;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+;* -- | | | '_ \| __| \___ \ Zurich University of -
+;* -- _| |_| | | | |____ ____) | Applied Sciences -
+;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+;* ------------------------------------------------------------------
+;* --
+;* -- Project : CT Board - Cortex M4
+;* -- Description : Data Segment initialisation.
+;* --
+;* -- $Id$
+;* ------------------------------------------------------------------
+
+
+; -------------------------------------------------------------------
+; -- __Main
+; -------------------------------------------------------------------
+
+ AREA |.text|, CODE, READONLY
+
+ IMPORT main
+
+ EXPORT __main
+
+__main PROC
+
+ ; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
+ IMPORT |Image$$RO$$Limit| [WEAK]
+ IMPORT |Image$$RW$$Base| [WEAK]
+ IMPORT |Image$$ZI$$Base| [WEAK]
+ IMPORT |Image$$ZI$$Limit| [WEAK]
+ ; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
+ IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
+ ; import stack parameter
+ IMPORT Stack_Size [WEAK]
+ IMPORT Stack_Mem [WEAK]
+
+ ; switch between command line generated regions and auto scatter file generated regions
+ LDR R1, =|Image$$RO$$Limit|
+ CMP R1,#0
+ BEQ ScatterFileSymbols
+CommandLineSymbols
+ LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
+ LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
+ MOV R5, R3 ; start of zero initialized data
+ LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
+ B CondRWLoop
+ScatterFileSymbols
+ LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
+ LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
+ LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
+ MOV R5, R3 ; start of zero initialized data
+ LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
+ B CondRWLoop
+
+ ; init non-zero data
+LoopRWCopy LDR R4, [R1]
+ STR R4, [R2]
+ ADDS R1, R1, #4
+ ADDS R2, R2, #4
+CondRWLoop CMP R2, R3
+ BNE LoopRWCopy
+
+ ; init zero-initialized data
+ MOV R2, R5
+ MOV R3, R6
+ MOVS R4, #0
+ B CondZILoop
+LoopZICopy STR R4, [R2]
+ ADDS R2, R2, #4
+CondZILoop CMP R2, R3
+ BNE LoopZICopy
+
+ ; fingerprint stack section
+ LDR R0, =Stack_Mem
+ LDR R1, =Stack_Size
+ LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
+LoopStack STR R2, [R0]
+ ADDS R0, R0, #4
+ SUBS R1, #4
+ BNE LoopStack
+
+ ; go to the user main function
+ LDR R0, =main
+ BX R0
+ ENDP
+
+
+; -------------------------------------------------------------------
+; -- End of file
+; -------------------------------------------------------------------
+
+ ALIGN
+
+ END
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 b/arith_operations/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1
new file mode 100644
index 0000000..fd8a0f9
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1
@@ -0,0 +1,439 @@
+;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
+;* File Name : startup_stm32f429_439xx.s
+;* Author : MCD Application Team
+;* Version : V1.3.0
+;* Date : 08-November-2013
+;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the system clock and the external SRAM/SDRAM mounted
+;* on STM324x9I-EVAL boards to be used as data memory
+;* (optional, to be enabled by user)
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00002000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Size
+ EXPORT Stack_Mem
+
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000800
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __system
+ IMPORT __main
+ ENTRY
+
+ LDR R0, =__system
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 b/arith_operations/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1
new file mode 100644
index 0000000..58c804c
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1
@@ -0,0 +1,290 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Interface of module system_ctboard.
+ * Description : Basic system configuration.
+ * * initialize system clock
+ * * initialize FMC (SRAM & GPIO)
+ *
+ * GPIO FMC pin assignment:
+ *
+ * PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
+ * PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
+ * PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
+ * PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
+ * PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
+ * PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
+ * PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
+ * PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
+ * PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
+ * PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
+ * PD11 > FMC_A16 | PE10 > FMC_D7 | |
+ * PD12 > FMC_A17 | PE11 > FMC_D8 | |
+ * PD13 > FMC_A18 | PE12 > FMC_D9 | |
+ * PD14 > FMC_D0 | PE13 > FMC_D10 | |
+ * PD15 > FMC_D1 | PE14 > FMC_D11 | |
+ * | PE15 > FMC_D12 | |
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* Standard includes */
+#include
+
+
+/* User includes */
+#include "system_ctboard.h"
+#include "reg_stm32f4xx.h"
+#include "reg_ctboard.h"
+
+
+/* -- Macros (LCD)
+ * ------------------------------------------------------------------------- */
+
+#define LCD_WAIT 0x1fff
+
+
+/* -- Macros (FMC)
+ * ------------------------------------------------------------------------- */
+
+#define FMC_PORTD_PINMASK 0xfffb
+#define FMC_PORTE_PINMASK 0xffff
+#define FMC_PORTF_PINMASK 0xf03f
+#define FMC_PORTG_PINMASK 0x363f
+
+
+/* -- Local function declarations
+ * ------------------------------------------------------------------------- */
+
+static void init_SystemClock(void);
+static void init_FPU(void);
+static void init_FMC_SRAM(void);
+static void init_LCD(void);
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Entry point used in startup.
+ */
+void __system(void)
+{
+ system_enter_run();
+}
+
+
+/*
+ * See header files
+ */
+void system_enter_run(void)
+{
+ /* Initialize RCC / system clock */
+ init_SystemClock();
+
+ /* Iitialize FPU */
+ init_FPU();
+
+ /* Initialize SRAM interface */
+ init_FMC_SRAM();
+
+ /* Initialize LCD on CT-Board */
+ init_LCD();
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_sleep(hal_pwr_lp_entry_t entry)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_standby(void)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/* -- Local function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Configures the System clock source, PLL Multiplier and Divider
+ * factors, AHB/APBx prescalers and Flash settings.
+ */
+static void init_SystemClock(void)
+{
+ hal_rcc_pll_init_t pll_init;
+ hal_rcc_clk_init_t clk_init;
+
+ /* Enable used periphery */
+ PWR_ENABLE();
+
+ /* Reset */
+ hal_rcc_reset();
+ PWR_RESET();
+
+ /* Enable HSE oscillator and proceed if ok */
+ if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
+ /* Select regulator voltage output Scale 1 mode */
+ RCC->APB1ENR |= 0x00000000;
+ PWR->CR |= 0x0000c000;
+
+ /* Configure PLL */
+ pll_init.source = HAL_RCC_OSC_HSE;
+ pll_init.m_divider = 4u;
+ pll_init.n_factor = 168u;
+ pll_init.p_divider = 2u;
+ pll_init.q_divider = 7u;
+ hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
+
+ /* Enable PLL */
+ hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
+
+ /* Enable overdrive to allow system clock >= 168 MHz */
+ hal_pwr_set_overdrive(ENABLE);
+
+ /* Configure Flash prefetch, Instruction cache, Data cache
+ * and wait state */
+ FLASH->ACR = 0x00000705;
+
+ /* Setup system clock */
+ clk_init.osc = HAL_RCC_OSC_PLL;
+ clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
+ clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
+ clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
+ hal_rcc_setup_clock(clk_init);
+
+ } else {
+ /* If HSE fails to start-up, the application will have wrong clock con-
+ figuration. User can add here some code to deal with this error */
+ }
+}
+
+
+/**
+ * \brief Initialize the floating point unit in M4 mode.
+ */
+static void init_FPU(void)
+{
+#ifdef PLATFORM_M4
+ /* No documentation about this, even the registers... */
+
+ /* set CP10 and CP11 Full Access */
+ FPU->CPACR |= ((3u << 20u)|(3u << 22u));
+#endif
+}
+
+
+/**
+ * \brief Setup the flexible memory controller. This function configures the SRAM
+ * interface for accessing the periphery on the CT Board.
+ */
+static void init_FMC_SRAM(void)
+{
+#ifndef NO_FMC
+
+ hal_gpio_output_t gpio_init;
+ hal_fmc_sram_init_t sram_init;
+ hal_fmc_sram_timing_t sram_timing;
+
+ /* Enable used peripherals */
+ GPIOD_ENABLE();
+ GPIOE_ENABLE();
+ GPIOF_ENABLE();
+ GPIOG_ENABLE();
+ FMC_ENABLE();
+
+ /* Configure the involved GPIO pins to AF12 (FMC) */
+ gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
+ gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
+ gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
+
+ /* GPIOD configuration (pins: 0,1,3-15) */
+ gpio_init.pins = FMC_PORTD_PINMASK;
+ hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOE configuration (pins: 0-15) */
+ gpio_init.pins = FMC_PORTE_PINMASK;
+ hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOF configuration (pins: 0-5,12-15) */
+ gpio_init.pins = FMC_PORTF_PINMASK;
+ hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
+ gpio_init.pins = FMC_PORTG_PINMASK;
+ hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
+
+
+ /* Initialize the synchronous PSRAM on bank 1 */
+ sram_init.address_mux = DISABLE;
+ sram_init.type = HAL_FMC_TYPE_PSRAM;
+ sram_init.width = HAL_FMC_WIDTH_16B;
+ sram_init.read_burst = ENABLE;
+ sram_init.write_enable = ENABLE;
+ sram_init.write_burst = ENABLE;
+ sram_init.continous_clock = ENABLE;
+
+ sram_timing.bus_turnaround = 1u;
+ sram_timing.clk_divider = 15u;
+ sram_timing.data_latency = 2u;
+
+ hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
+
+
+ /* Initialize the asynchronous SRAM on bank 2 */
+ sram_init.address_mux = DISABLE;
+ sram_init.type = HAL_FMC_TYPE_SRAM;
+ sram_init.width = HAL_FMC_WIDTH_16B;
+ sram_init.read_burst = DISABLE;
+ sram_init.write_enable = DISABLE;
+ sram_init.write_burst = DISABLE;
+ sram_init.continous_clock = DISABLE;
+
+ sram_timing.bus_turnaround = 1u;
+ sram_timing.address_setup = 11u;
+ sram_timing.address_hold = 5u;
+ sram_timing.data_setup = 11u;
+ sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
+
+ hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
+
+#endif
+}
+
+
+/**
+ * \brief Wait for the LCD controller on the CT Board to be initialized.
+ * \TODO Possibly adjust LCD controller on CPLD to set status bit
+ * and wait for it in this function.
+ */
+static void init_LCD(void)
+{
+#ifndef NO_FMC
+ uint32_t wait_for_lcd = LCD_WAIT;
+ for(; wait_for_lcd > 0; wait_for_lcd--);
+#endif
+}
+
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s b/arith_operations/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
new file mode 100644
index 0000000..d891d1a
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
@@ -0,0 +1,100 @@
+;* ------------------------------------------------------------------
+;* -- _____ ______ _____ -
+;* -- |_ _| | ____|/ ____| -
+;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+;* -- | | | '_ \| __| \___ \ Zurich University of -
+;* -- _| |_| | | | |____ ____) | Applied Sciences -
+;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+;* ------------------------------------------------------------------
+;* --
+;* -- Project : CT Board - Cortex M4
+;* -- Description : Data Segment initialisation.
+;* --
+;* -- $Id$
+;* ------------------------------------------------------------------
+
+
+; -------------------------------------------------------------------
+; -- __Main
+; -------------------------------------------------------------------
+
+ AREA |.text|, CODE, READONLY
+
+ IMPORT main
+
+ EXPORT __main
+
+__main PROC
+
+ ; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
+ IMPORT |Image$$RO$$Limit| [WEAK]
+ IMPORT |Image$$RW$$Base| [WEAK]
+ IMPORT |Image$$ZI$$Base| [WEAK]
+ IMPORT |Image$$ZI$$Limit| [WEAK]
+ ; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
+ IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
+ IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
+ ; import stack parameter
+ IMPORT Stack_Size [WEAK]
+ IMPORT Stack_Mem [WEAK]
+
+ ; switch between command line generated regions and auto scatter file generated regions
+ LDR R1, =|Image$$RO$$Limit|
+ CMP R1,#0
+ BEQ ScatterFileSymbols
+CommandLineSymbols
+ LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
+ LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
+ MOV R5, R3 ; start of zero initialized data
+ LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
+ B CondRWLoop
+ScatterFileSymbols
+ LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
+ LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
+ LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
+ MOV R5, R3 ; start of zero initialized data
+ LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
+ B CondRWLoop
+
+ ; init non-zero data
+LoopRWCopy LDR R4, [R1]
+ STR R4, [R2]
+ ADDS R1, R1, #4
+ ADDS R2, R2, #4
+CondRWLoop CMP R2, R3
+ BNE LoopRWCopy
+
+ ; init zero-initialized data
+ MOV R2, R5
+ MOV R3, R6
+ MOVS R4, #0
+ B CondZILoop
+LoopZICopy STR R4, [R2]
+ ADDS R2, R2, #4
+CondZILoop CMP R2, R3
+ BNE LoopZICopy
+
+ ; fingerprint stack section
+ LDR R0, =Stack_Mem
+ LDR R1, =Stack_Size
+ LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
+LoopStack STR R2, [R0]
+ ADDS R0, R0, #4
+ SUBS R1, #4
+ BNE LoopStack
+
+ ; go to the user main function
+ LDR R0, =main
+ BX R0
+ ENDP
+
+
+; -------------------------------------------------------------------
+; -- End of file
+; -------------------------------------------------------------------
+
+ ALIGN
+
+ END
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s b/arith_operations/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
new file mode 100644
index 0000000..fd8a0f9
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/startup_ctboard.s
@@ -0,0 +1,439 @@
+;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
+;* File Name : startup_stm32f429_439xx.s
+;* Author : MCD Application Team
+;* Version : V1.3.0
+;* Date : 08-November-2013
+;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the system clock and the external SRAM/SDRAM mounted
+;* on STM324x9I-EVAL boards to be used as data memory
+;* (optional, to be enabled by user)
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00002000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Size
+ EXPORT Stack_Mem
+
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000800
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __system
+ IMPORT __main
+ ENTRY
+
+ LDR R0, =__system
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/arith_operations/RTE/Device/CT_Board_HS14_M0/system_ctboard.c b/arith_operations/RTE/Device/CT_Board_HS14_M0/system_ctboard.c
new file mode 100644
index 0000000..58c804c
--- /dev/null
+++ b/arith_operations/RTE/Device/CT_Board_HS14_M0/system_ctboard.c
@@ -0,0 +1,290 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Interface of module system_ctboard.
+ * Description : Basic system configuration.
+ * * initialize system clock
+ * * initialize FMC (SRAM & GPIO)
+ *
+ * GPIO FMC pin assignment:
+ *
+ * PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
+ * PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
+ * PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
+ * PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
+ * PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
+ * PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
+ * PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
+ * PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
+ * PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
+ * PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
+ * PD11 > FMC_A16 | PE10 > FMC_D7 | |
+ * PD12 > FMC_A17 | PE11 > FMC_D8 | |
+ * PD13 > FMC_A18 | PE12 > FMC_D9 | |
+ * PD14 > FMC_D0 | PE13 > FMC_D10 | |
+ * PD15 > FMC_D1 | PE14 > FMC_D11 | |
+ * | PE15 > FMC_D12 | |
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* Standard includes */
+#include
+
+
+/* User includes */
+#include "system_ctboard.h"
+#include "reg_stm32f4xx.h"
+#include "reg_ctboard.h"
+
+
+/* -- Macros (LCD)
+ * ------------------------------------------------------------------------- */
+
+#define LCD_WAIT 0x1fff
+
+
+/* -- Macros (FMC)
+ * ------------------------------------------------------------------------- */
+
+#define FMC_PORTD_PINMASK 0xfffb
+#define FMC_PORTE_PINMASK 0xffff
+#define FMC_PORTF_PINMASK 0xf03f
+#define FMC_PORTG_PINMASK 0x363f
+
+
+/* -- Local function declarations
+ * ------------------------------------------------------------------------- */
+
+static void init_SystemClock(void);
+static void init_FPU(void);
+static void init_FMC_SRAM(void);
+static void init_LCD(void);
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Entry point used in startup.
+ */
+void __system(void)
+{
+ system_enter_run();
+}
+
+
+/*
+ * See header files
+ */
+void system_enter_run(void)
+{
+ /* Initialize RCC / system clock */
+ init_SystemClock();
+
+ /* Iitialize FPU */
+ init_FPU();
+
+ /* Initialize SRAM interface */
+ init_FMC_SRAM();
+
+ /* Initialize LCD on CT-Board */
+ init_LCD();
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_sleep(hal_pwr_lp_entry_t entry)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/*
+ * See header file
+ */
+void system_enter_standby(void)
+{
+ /** \note Implement this function if needed. */
+}
+
+
+/* -- Local function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Configures the System clock source, PLL Multiplier and Divider
+ * factors, AHB/APBx prescalers and Flash settings.
+ */
+static void init_SystemClock(void)
+{
+ hal_rcc_pll_init_t pll_init;
+ hal_rcc_clk_init_t clk_init;
+
+ /* Enable used periphery */
+ PWR_ENABLE();
+
+ /* Reset */
+ hal_rcc_reset();
+ PWR_RESET();
+
+ /* Enable HSE oscillator and proceed if ok */
+ if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
+ /* Select regulator voltage output Scale 1 mode */
+ RCC->APB1ENR |= 0x00000000;
+ PWR->CR |= 0x0000c000;
+
+ /* Configure PLL */
+ pll_init.source = HAL_RCC_OSC_HSE;
+ pll_init.m_divider = 4u;
+ pll_init.n_factor = 168u;
+ pll_init.p_divider = 2u;
+ pll_init.q_divider = 7u;
+ hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
+
+ /* Enable PLL */
+ hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
+
+ /* Enable overdrive to allow system clock >= 168 MHz */
+ hal_pwr_set_overdrive(ENABLE);
+
+ /* Configure Flash prefetch, Instruction cache, Data cache
+ * and wait state */
+ FLASH->ACR = 0x00000705;
+
+ /* Setup system clock */
+ clk_init.osc = HAL_RCC_OSC_PLL;
+ clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
+ clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
+ clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
+ hal_rcc_setup_clock(clk_init);
+
+ } else {
+ /* If HSE fails to start-up, the application will have wrong clock con-
+ figuration. User can add here some code to deal with this error */
+ }
+}
+
+
+/**
+ * \brief Initialize the floating point unit in M4 mode.
+ */
+static void init_FPU(void)
+{
+#ifdef PLATFORM_M4
+ /* No documentation about this, even the registers... */
+
+ /* set CP10 and CP11 Full Access */
+ FPU->CPACR |= ((3u << 20u)|(3u << 22u));
+#endif
+}
+
+
+/**
+ * \brief Setup the flexible memory controller. This function configures the SRAM
+ * interface for accessing the periphery on the CT Board.
+ */
+static void init_FMC_SRAM(void)
+{
+#ifndef NO_FMC
+
+ hal_gpio_output_t gpio_init;
+ hal_fmc_sram_init_t sram_init;
+ hal_fmc_sram_timing_t sram_timing;
+
+ /* Enable used peripherals */
+ GPIOD_ENABLE();
+ GPIOE_ENABLE();
+ GPIOF_ENABLE();
+ GPIOG_ENABLE();
+ FMC_ENABLE();
+
+ /* Configure the involved GPIO pins to AF12 (FMC) */
+ gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
+ gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
+ gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
+
+ /* GPIOD configuration (pins: 0,1,3-15) */
+ gpio_init.pins = FMC_PORTD_PINMASK;
+ hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOE configuration (pins: 0-15) */
+ gpio_init.pins = FMC_PORTE_PINMASK;
+ hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOF configuration (pins: 0-5,12-15) */
+ gpio_init.pins = FMC_PORTF_PINMASK;
+ hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
+
+ /* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
+ gpio_init.pins = FMC_PORTG_PINMASK;
+ hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
+
+
+ /* Initialize the synchronous PSRAM on bank 1 */
+ sram_init.address_mux = DISABLE;
+ sram_init.type = HAL_FMC_TYPE_PSRAM;
+ sram_init.width = HAL_FMC_WIDTH_16B;
+ sram_init.read_burst = ENABLE;
+ sram_init.write_enable = ENABLE;
+ sram_init.write_burst = ENABLE;
+ sram_init.continous_clock = ENABLE;
+
+ sram_timing.bus_turnaround = 1u;
+ sram_timing.clk_divider = 15u;
+ sram_timing.data_latency = 2u;
+
+ hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
+
+
+ /* Initialize the asynchronous SRAM on bank 2 */
+ sram_init.address_mux = DISABLE;
+ sram_init.type = HAL_FMC_TYPE_SRAM;
+ sram_init.width = HAL_FMC_WIDTH_16B;
+ sram_init.read_burst = DISABLE;
+ sram_init.write_enable = DISABLE;
+ sram_init.write_burst = DISABLE;
+ sram_init.continous_clock = DISABLE;
+
+ sram_timing.bus_turnaround = 1u;
+ sram_timing.address_setup = 11u;
+ sram_timing.address_hold = 5u;
+ sram_timing.data_setup = 11u;
+ sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
+
+ hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
+
+#endif
+}
+
+
+/**
+ * \brief Wait for the LCD controller on the CT Board to be initialized.
+ * \TODO Possibly adjust LCD controller on CPLD to set status bit
+ * and wait for it in this function.
+ */
+static void init_LCD(void)
+{
+#ifndef NO_FMC
+ uint32_t wait_for_lcd = LCD_WAIT;
+ for(; wait_for_lcd > 0; wait_for_lcd--);
+#endif
+}
+
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1
new file mode 100644
index 0000000..e454145
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_fmc.
+ *
+ * The hardware abstraction layer for the memory controller.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_fmc.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define MASK_PERIPH_FMC (0x00000001)
+#define MASK_SRAM_ENABLE (0x00000001)
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_fmc_reset(hal_fmc_bank_t bank)
+{
+ switch (bank) {
+ default:
+ case HAL_FMC_SRAM_BANK1:
+ FMC->SRAM.BCR1 = 0x000030db;
+ FMC->SRAM.BTR1 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK2:
+ FMC->SRAM.BCR2 = 0x000030d2;
+ FMC->SRAM.BTR2 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK3:
+ FMC->SRAM.BCR3 = 0x000030d2;
+ FMC->SRAM.BTR3 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK4:
+ FMC->SRAM.BCR4 = 0x000030d2;
+ FMC->SRAM.BTR4 = 0x0fffffff;
+ break;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_fmc_init_sram(hal_fmc_bank_t bank,
+ hal_fmc_sram_init_t init,
+ hal_fmc_sram_timing_t timing)
+{
+ uint32_t reg_cr = 0, reg_tr = 0;
+
+ /* Input check */
+ timing.address_setup &= 0xf;
+ timing.address_hold &= 0xf;
+ if (timing.address_hold < 1u) timing.address_hold = 1u;
+ timing.data_setup &= 0xff;
+ if (timing.data_setup < 1u) timing.data_setup = 1u;
+ timing.bus_turnaround &= 0xf;
+
+ /* Input check clock divider (2..16) */
+ if (timing.clk_divider > 16u) timing.clk_divider = 16u;
+ if (timing.clk_divider < 2u) timing.clk_divider = 2u;
+ timing.clk_divider -= 1u; // 0b0001 -> clk / 2
+
+ /* Input check data latency (2..17) */
+ if (timing.data_latency > 17u) timing.data_latency = 17u;
+ if (timing.data_latency < 2u) timing.data_latency = 2u;
+ timing.data_latency -= 2u; // 0b0000 -> latency = 2
+
+ /* Process boolean parameter */
+ if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
+ if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
+ if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
+ if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
+ if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
+
+ /* Process non boolean parameter */
+ reg_cr |= (init.type << 2u);
+ reg_cr |= (init.width << 4u);
+
+ /* Process timing for async. SRAM */
+ if (init.type == HAL_FMC_TYPE_SRAM) {
+ reg_tr |= (timing.address_setup << 0u);
+ reg_tr |= (timing.address_hold << 4u);
+ reg_tr |= (timing.data_setup << 8u);
+ reg_tr |= (timing.mode << 28u);
+ }
+ /* Process timing for sync. PSRAM */
+ else if (init.type == HAL_FMC_TYPE_PSRAM) {
+ reg_tr |= (timing.clk_divider << 20u);
+ reg_tr |= (timing.data_latency << 24u);
+ }
+ /* Process bus turnaround time */
+ reg_tr |= (timing.bus_turnaround << 16u);
+
+ /* Write register */
+ switch (bank) {
+ default:
+ case HAL_FMC_SRAM_BANK1:
+ FMC->SRAM.BCR1 = reg_cr;
+ FMC->SRAM.BTR1 = reg_tr;
+ FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK2:
+ FMC->SRAM.BCR2 = reg_cr;
+ FMC->SRAM.BTR2 = reg_tr;
+ FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK3:
+ FMC->SRAM.BCR3 = reg_cr;
+ FMC->SRAM.BTR3 = reg_tr;
+ FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK4:
+ FMC->SRAM.BCR4 = reg_cr;
+ FMC->SRAM.BTR4 = reg_tr;
+ FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
+ break;
+ }
+}
+
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1
new file mode 100644
index 0000000..59e0e4c
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1
@@ -0,0 +1,412 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_gpio.
+ *
+ * The hardware abstraction layer for the GPIO periphery.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_gpio.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define NVIC_OFFSET_1_4 ( 6u)
+#define NVIC_OFFSET_5_9 (23u)
+#define NVIC_OFFSET_10_15 ( 8u)
+
+
+/* -- Local function declarations
+ * ------------------------------------------------------------------------- */
+
+static uint32_t create_pattern_mask(uint16_t pins,
+ uint8_t pattern,
+ uint8_t pattern_bit_width);
+static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
+static uint8_t get_syscfg_mask(reg_gpio_t *port);
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_gpio_reset(reg_gpio_t *port)
+{
+ if(port == GPIOA) {
+ /* Reset GPIOA specific values */
+ port->MODER = 0xa8000000;
+ port->OSPEEDR = 0x00000000;
+ port->PUPDR = 0x64000000;
+ }
+ else if (port == GPIOB) {
+ /* Reset GPIOB specific values */
+ port->MODER = 0x00000280;
+ port->OSPEEDR = 0x000000c0;
+ port->PUPDR = 0x00000100;
+ } else {
+ /* Reset other GPIO */
+ port->MODER = 0x00000000;
+ port->OSPEEDR = 0x00000000;
+ port->PUPDR = 0x00000000;
+ }
+
+ port->OTYPER = 0x00000000;
+ port->AFRL = 0x00000000;
+ port->AFRH = 0x00000000;
+ port->ODR = 0x00000000;
+}
+
+/*
+ * See header file
+ */
+void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
+{
+ /* prevent overwrite false reg entry */
+ init.pins = intercept_overwrite_register(port, init.pins);
+
+ /* process mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
+
+ /* process pull up/down resitors */
+ port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
+{
+ /* treat like input */
+ hal_gpio_init_input(port, init);
+
+ /* change mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
+{
+ /* prevent overwrite false reg entry */
+ init.pins = intercept_overwrite_register(port, init.pins);
+
+ /* process mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
+
+ /* process pull up/down resitors */
+ port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
+
+ /* process port speed */
+ port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
+
+ /* process output typ */
+ port->OTYPER &= ~init.pins;
+ if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
+ port->OTYPER |= init.pins;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_alternate(reg_gpio_t *port,
+ hal_gpio_af_t af_mode,
+ hal_gpio_output_t init)
+{
+ /* treat like output */
+ hal_gpio_init_output(port, init);
+
+ /* change mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
+
+ /* process af type */
+ port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
+ port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
+ port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
+ port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
+}
+
+
+/*
+ * See header file
+ */
+uint16_t hal_gpio_input_read(reg_gpio_t *port)
+{
+ return (uint16_t) port->IDR;
+}
+
+
+/*
+ * See header file
+ */
+uint16_t hal_gpio_output_read(reg_gpio_t *port)
+{
+ return (uint16_t) port->ODR;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
+{
+ /* prevent overwrite false reg entry */
+ port_value = intercept_overwrite_register(port, port_value);
+ port->ODR = port_value;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
+{
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ port->BSRR = pins;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
+{
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ port->BSRR = (pins << 16);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
+{
+ uint16_t pattern;
+
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ /* get actual value and invert */
+ pattern = hal_gpio_output_read(port);
+ pattern = ~pattern;
+
+ /* mask pins */
+ pattern &= pins;
+
+ port->ODR = pattern;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_irq_set(reg_gpio_t *port,
+ uint16_t pins,
+ hal_gpio_trg_t edge,
+ hal_bool_t status)
+{
+ uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
+ uint32_t exticr_mask;
+
+ for (exti_line = 0u; exti_line < 16u; exti_line++) {
+ if (pins & (0x1 << exti_line)) {
+ syscfg_bank = exti_line / 4u;
+ syscfg_shift = exti_line % 4u;
+ nvic_bank = (exti_line < 10u) ? 0u : 1u;
+
+ if (status == ENABLE) {
+ /* Trigger (rising/falling/both) */
+ if (edge & HAL_GPIO_TRG_POS) {
+ EXTI->RTSR |= (0x1 << exti_line);
+ }
+ if (edge & HAL_GPIO_TRG_NEG) {
+ EXTI->FTSR |= (0x1 << exti_line);
+ }
+ /* Set EXTI line to corresponding GPIO port */
+ exticr_mask = get_syscfg_mask(port);
+ if (syscfg_bank == 0u) {
+ SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 1u) {
+ SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 2u) {
+ SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 3u) {
+ SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
+ }
+
+ /* Unmask interrupt */
+ EXTI->IMR |= (0x1 << exti_line);
+ if (nvic_bank == 0u) {
+ NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 1u) {
+ NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 2u) {
+ NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ }
+
+ } else {
+ /* Mask interrupt */
+ EXTI->IMR &= ~(0x1 << exti_line);
+ if (nvic_bank == 0u) {
+ NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 1u) {
+ NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 2u) {
+ NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ }
+ }
+ }
+ }
+
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_gpio_irq_status(uint16_t pin)
+{
+ hal_bool_t status = DISABLED;
+
+ if ((EXTI->IMR && pin) &&
+ (EXTI->PR && pin)) {
+ status = ENABLED;
+ }
+
+ return status;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_irq_clear(uint16_t pin)
+{
+ EXTI->PR |= pin;
+}
+
+
+/* -- Local function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Creates a pattern based on specified pins.
+ *
+ * example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
+ * ==> pattern = 0x0000'0288
+ *
+ * 0b0..0'0001'1010 / 0b10 (2 bit wide)
+ * ^ ^ ^
+ * ==> 0b0..0'00010'1000'1000
+ * ^^ ^^ ^^
+ *
+ * pattern_bit_width must be 2 or 4
+ */
+static uint32_t create_pattern_mask(uint16_t pins,
+ uint8_t pattern,
+ uint8_t pattern_bit_width)
+{
+ const uint8_t mask_bit_width = 32u;
+ const uint16_t pin1_mask = 1u;
+
+ uint8_t pos, end;
+ uint32_t mask = 0u;
+
+ if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
+ /* create pattern mask */
+ end = mask_bit_width / pattern_bit_width;
+ for (pos = 0; pos < end; pos++) {
+ if (pins & pin1_mask) {
+ mask |= pattern << (pos * pattern_bit_width);
+ }
+ pins >>= 1;
+ }
+ } else {
+ /* exit if pattern_bit_width not as needed */
+ mask = 0u;
+ }
+
+ return mask;
+}
+
+
+/**
+ * \brief This function ensures that these sensitive pins are not reconfigured.
+ *
+ * On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
+ * Pins 15 down to 12 are used for system functions of the discovery board,
+ * e.g. connection of the debugger.
+ * These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
+ */
+static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
+ if (port == GPIOA || port == GPIOB){
+ pins &= 0x0FFF;
+ }
+ return pins;
+}
+
+
+/**
+ * \brief Returns mask for configuration of SYSCFG_EXTICR register.
+ * \param port : Port of which the mask should be generated.
+ * \return Mask for specified port.
+ */
+static uint8_t get_syscfg_mask(reg_gpio_t *port)
+{
+ return ((port == GPIOA) ? 0u :
+ (port == GPIOB) ? 1u :
+ (port == GPIOC) ? 2u :
+ (port == GPIOD) ? 3u :
+ (port == GPIOE) ? 4u :
+ (port == GPIOF) ? 5u :
+ (port == GPIOG) ? 6u :
+ (port == GPIOH) ? 7u :
+ (port == GPIOI) ? 8u :
+ (port == GPIOJ) ? 9u : 10u);
+}
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0
new file mode 100644
index 0000000..a244dd6
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_pwr.
+ *
+ * The hardware abstraction layer for the power control unit.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_pwr.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define TIME_OUT 0x1000
+#define MASK_PERIPH_PWR (1u << 28u)
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_pwr_reset(void)
+{
+ /* Reset peripheral */
+ PWR->CR = 0x0000c000;
+ PWR->CSR = 0x00000000;
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
+{
+ uint16_t count = 0;
+ uint32_t reg = 0;
+
+ if (status == DISABLE) {
+ /* Disable backup domain / regulator */
+ PWR->CSR &= ~(1u << 9u);
+ return DISABLED;
+ }
+
+ /* Enable backup domain / regulator */
+ PWR->CSR |= (1u << 9u);
+
+ /* Wait till regulator is ready and if time out is reached exit */
+ reg = PWR->CSR & (1u << 3u);
+ while ((reg == 0) && (count != TIME_OUT)) {
+ reg = PWR->CSR & (1u << 3u);
+ count++;
+ }
+
+ /* Return */
+ if (reg != 0) {
+ return ENABLED;
+ }
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_backup_access(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CR &= ~(1u << 8u);
+ } else {
+ PWR->CR |= (1u << 8u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_wakeup_pin(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CSR &= ~(1u << 8u);
+ } else {
+ PWR->CSR |= (1u << 8u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_flash_powerdown(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CR &= ~(1u << 9u);
+ } else {
+ PWR->CR |= (1u << 9u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
+{
+ /* Is this realy nedded ?
+ Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
+{
+ /* Is this realy nedded ? */
+ return DISABLED;
+}
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1
new file mode 100644
index 0000000..fdd4d3a
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1
@@ -0,0 +1,347 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_rcc.
+ *
+ * The hardware abstraction layer for the reset and clock control unit.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_rcc.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define TIME_OUT 0x5000
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_rcc_reset(void)
+{
+ /* Set RCC->CR to default values */
+ RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
+ RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
+ // PLLSAI bits (STM32F42xx/43xx)
+ RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
+
+ /* Reset RCC->CFGR to default values */
+ RCC->CFGR = 0u;
+
+ /* Reset RCC->PLLxCFGR to default values */
+ RCC->PLLCFGR = 0x24003010;
+ RCC->PLLI2SCFGR = 0x20003000;
+ RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
+
+ /* Disable all interrupts */
+ RCC->CIR = 0u;
+
+ /* Disable all peripherals */
+ RCC->AHB1RSTR = 0u;
+ RCC->AHB2RSTR = 0u;
+ RCC->AHB3RSTR = 0u;
+ RCC->APB1RSTR = 0u;
+ RCC->APB2RSTR = 0u;
+ RCC->AHB1ENR = 0x00100000;
+ RCC->AHB2ENR = 0u;
+ RCC->AHB3ENR = 0u;
+ RCC->APB1ENR = 0u;
+ RCC->APB2ENR = 0u;
+ RCC->AHB1LPENR = 0x7e6791ff;
+ RCC->AHB2LPENR = 0x000000f1;
+ RCC->AHB3LPENR = 0x00000001;
+ RCC->APB1LPENR = 0x36fec9ff;
+ RCC->APB2LPENR = 0x00075f33;
+
+ /* Reset forgotten registers */
+ RCC->BDCR = 0u;
+ RCC->CSR = 0x0e000000;
+ RCC->SSCGR = 0u;
+ RCC->DCKCFGR = 0u;
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
+{
+ volatile uint32_t *reg;
+ uint32_t bit_pos;
+
+ /* Select correct enable register */
+ switch (peripheral) {
+ /* AHB1 */
+ case PER_GPIOA:
+ bit_pos = 0u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOB:
+ bit_pos = 1u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOC:
+ bit_pos = 2u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOD:
+ bit_pos = 3u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOE:
+ bit_pos = 4u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOF:
+ bit_pos = 5u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOG:
+ bit_pos = 6u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOH:
+ bit_pos = 7u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOI:
+ bit_pos = 8u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOJ:
+ bit_pos = 9u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOK:
+ bit_pos = 10u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_DMA1:
+ bit_pos = 21u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_DMA2:
+ bit_pos = 22u;
+ reg = &RCC->AHB1ENR;
+ break;
+
+ /* AHB3 */
+ case PER_FMC:
+ bit_pos = 0u;
+ reg = &RCC->AHB3ENR;
+ break;
+
+ /* APB1 */
+ case PER_DAC:
+ bit_pos = 29u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_PWR:
+ bit_pos = 28u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM2:
+ bit_pos = 0u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM3:
+ bit_pos = 1u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM4:
+ bit_pos = 2u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM5:
+ bit_pos = 3u;
+ reg = &RCC->APB1ENR;
+ break;
+
+
+ /* APB2 */
+ case PER_ADC1:
+ bit_pos = 8u;
+ reg = &RCC->APB2ENR;
+ break;
+ case PER_ADC2:
+ bit_pos = 9u;
+ reg = &RCC->APB2ENR;
+ break;
+ case PER_ADC3:
+ bit_pos = 10u;
+ reg = &RCC->APB2ENR;
+ break;
+
+ default:
+ return;
+ }
+
+ if (status == DISABLE) {
+ *reg &= ~(1u << bit_pos);
+ } else {
+ *reg |= (1u << bit_pos);
+ }
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
+{
+ uint32_t reg = 0;
+ uint32_t count = 0;
+
+ /* Disable source */
+ if (status == DISABLE) {
+ RCC->CR &= ~(1u << source);
+ return DISABLED;
+ }
+
+ /* If pll, check if source is ok */
+ if (source == HAL_RCC_OSC_PLL ||
+ source == HAL_RCC_OSC_PLLI2S ||
+ source == HAL_RCC_OSC_PLLSAI)
+ {
+ reg = RCC->CR;
+ /* HSE */
+ if (RCC->PLLCFGR & ~(1u << 22u)) {
+ reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
+ }
+ /* HSI */
+ else {
+ reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
+ }
+ /* Return if source is not ok */
+ if (!reg) {
+ return DISABLED;
+ }
+ }
+
+ /* Enable source */
+ RCC->CR |= (1u << source);
+
+ /* Wait till source is ready and if time out is reached exit */
+ reg = RCC->CR & (1u << (source + 1u));
+ while ((reg == 0) && (count != TIME_OUT)) {
+ reg = RCC->CR & (1u << (source + 1u));
+ count++;
+ }
+
+ /* Return */
+ if (reg != 0) {
+ return ENABLED;
+ }
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
+{
+ /* Input check */
+ if (init.m_divider < 2u) init.m_divider = 2u;
+
+ if (init.n_factor < 2u) init.n_factor = 2u;
+ if (init.n_factor > 432u) init.n_factor = 432u;
+
+ if (init.p_divider > 8u) init.p_divider = 8u;
+
+ if (init.q_divider < 2u) init.q_divider = 2u;
+
+ init.r_divider &= 0x07;
+
+ /* Set source or return if invalid */
+ if (init.source == HAL_RCC_OSC_HSI) {
+ RCC->PLLCFGR &= ~(1u << 22u);
+ } else if (init.source == HAL_RCC_OSC_HSE) {
+ RCC->PLLCFGR |= (1u << 22u);
+ } else {
+ return;
+ }
+
+ /* Set pll preescaler */
+ RCC->PLLCFGR &= ~(0x3f);
+ RCC->PLLCFGR |= init.m_divider;
+
+ /* Configure pll */
+ switch (pll) {
+ case HAL_RCC_OSC_PLL:
+ RCC->PLLCFGR &= ~0x0f037fc0;
+ RCC->PLLCFGR |= (init.n_factor << 6u);
+ RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
+ RCC->PLLCFGR |= (init.q_divider << 24u);
+ break;
+
+ case HAL_RCC_OSC_PLLI2S:
+ RCC->PLLI2SCFGR &= ~0x7f007fc0;
+ RCC->PLLI2SCFGR |= (init.n_factor << 6u);
+ RCC->PLLI2SCFGR |= (init.q_divider << 24u);
+ RCC->PLLI2SCFGR |= (init.r_divider << 28u);
+ break;
+
+/* case HAL_RCC_OSC_PLLSAI:
+ RCC->PLLSAICFGR &= ~0x7f007fc0;
+ RCC->PLLSAICFGR |= (init.n_factor << 6u);
+ RCC->PLLSAICFGR |= (init.q_divider << 24u);
+ RCC->PLLSAICFGR |= (init.r_divider << 28u);
+ break;
+*/
+ default:
+ break;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
+{
+ uint32_t reg = 0;
+
+ /* Configure clock divider */
+ RCC->CFGR &= ~0x0000fcf0;
+ RCC->CFGR |= (init.hpre << 4u);
+ RCC->CFGR |= (init.ppre1 << 10u);
+ RCC->CFGR |= (init.ppre2 << 13u);
+
+ /* Select system clock source */
+ RCC->CFGR &= ~0x00000003;
+ switch (init.osc) {
+ default:
+ case HAL_RCC_OSC_HSI:
+ reg = 0u;
+ break;
+
+ case HAL_RCC_OSC_HSE:
+ reg = 1u;
+ break;
+
+ case HAL_RCC_OSC_PLL:
+ reg = 2u;
+ break;
+ }
+ RCC->CFGR |= reg;
+
+#ifndef TESTING
+ /* Wait till system clock is selected */
+ while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
+#endif
+}
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c
new file mode 100644
index 0000000..e454145
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_fmc.
+ *
+ * The hardware abstraction layer for the memory controller.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_fmc.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define MASK_PERIPH_FMC (0x00000001)
+#define MASK_SRAM_ENABLE (0x00000001)
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_fmc_reset(hal_fmc_bank_t bank)
+{
+ switch (bank) {
+ default:
+ case HAL_FMC_SRAM_BANK1:
+ FMC->SRAM.BCR1 = 0x000030db;
+ FMC->SRAM.BTR1 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK2:
+ FMC->SRAM.BCR2 = 0x000030d2;
+ FMC->SRAM.BTR2 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK3:
+ FMC->SRAM.BCR3 = 0x000030d2;
+ FMC->SRAM.BTR3 = 0x0fffffff;
+ break;
+
+ case HAL_FMC_SRAM_BANK4:
+ FMC->SRAM.BCR4 = 0x000030d2;
+ FMC->SRAM.BTR4 = 0x0fffffff;
+ break;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_fmc_init_sram(hal_fmc_bank_t bank,
+ hal_fmc_sram_init_t init,
+ hal_fmc_sram_timing_t timing)
+{
+ uint32_t reg_cr = 0, reg_tr = 0;
+
+ /* Input check */
+ timing.address_setup &= 0xf;
+ timing.address_hold &= 0xf;
+ if (timing.address_hold < 1u) timing.address_hold = 1u;
+ timing.data_setup &= 0xff;
+ if (timing.data_setup < 1u) timing.data_setup = 1u;
+ timing.bus_turnaround &= 0xf;
+
+ /* Input check clock divider (2..16) */
+ if (timing.clk_divider > 16u) timing.clk_divider = 16u;
+ if (timing.clk_divider < 2u) timing.clk_divider = 2u;
+ timing.clk_divider -= 1u; // 0b0001 -> clk / 2
+
+ /* Input check data latency (2..17) */
+ if (timing.data_latency > 17u) timing.data_latency = 17u;
+ if (timing.data_latency < 2u) timing.data_latency = 2u;
+ timing.data_latency -= 2u; // 0b0000 -> latency = 2
+
+ /* Process boolean parameter */
+ if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
+ if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
+ if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
+ if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
+ if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
+
+ /* Process non boolean parameter */
+ reg_cr |= (init.type << 2u);
+ reg_cr |= (init.width << 4u);
+
+ /* Process timing for async. SRAM */
+ if (init.type == HAL_FMC_TYPE_SRAM) {
+ reg_tr |= (timing.address_setup << 0u);
+ reg_tr |= (timing.address_hold << 4u);
+ reg_tr |= (timing.data_setup << 8u);
+ reg_tr |= (timing.mode << 28u);
+ }
+ /* Process timing for sync. PSRAM */
+ else if (init.type == HAL_FMC_TYPE_PSRAM) {
+ reg_tr |= (timing.clk_divider << 20u);
+ reg_tr |= (timing.data_latency << 24u);
+ }
+ /* Process bus turnaround time */
+ reg_tr |= (timing.bus_turnaround << 16u);
+
+ /* Write register */
+ switch (bank) {
+ default:
+ case HAL_FMC_SRAM_BANK1:
+ FMC->SRAM.BCR1 = reg_cr;
+ FMC->SRAM.BTR1 = reg_tr;
+ FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK2:
+ FMC->SRAM.BCR2 = reg_cr;
+ FMC->SRAM.BTR2 = reg_tr;
+ FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK3:
+ FMC->SRAM.BCR3 = reg_cr;
+ FMC->SRAM.BTR3 = reg_tr;
+ FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
+ break;
+
+ case HAL_FMC_SRAM_BANK4:
+ FMC->SRAM.BCR4 = reg_cr;
+ FMC->SRAM.BTR4 = reg_tr;
+ FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
+ break;
+ }
+}
+
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c
new file mode 100644
index 0000000..59e0e4c
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c
@@ -0,0 +1,412 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_gpio.
+ *
+ * The hardware abstraction layer for the GPIO periphery.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_gpio.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define NVIC_OFFSET_1_4 ( 6u)
+#define NVIC_OFFSET_5_9 (23u)
+#define NVIC_OFFSET_10_15 ( 8u)
+
+
+/* -- Local function declarations
+ * ------------------------------------------------------------------------- */
+
+static uint32_t create_pattern_mask(uint16_t pins,
+ uint8_t pattern,
+ uint8_t pattern_bit_width);
+static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
+static uint8_t get_syscfg_mask(reg_gpio_t *port);
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_gpio_reset(reg_gpio_t *port)
+{
+ if(port == GPIOA) {
+ /* Reset GPIOA specific values */
+ port->MODER = 0xa8000000;
+ port->OSPEEDR = 0x00000000;
+ port->PUPDR = 0x64000000;
+ }
+ else if (port == GPIOB) {
+ /* Reset GPIOB specific values */
+ port->MODER = 0x00000280;
+ port->OSPEEDR = 0x000000c0;
+ port->PUPDR = 0x00000100;
+ } else {
+ /* Reset other GPIO */
+ port->MODER = 0x00000000;
+ port->OSPEEDR = 0x00000000;
+ port->PUPDR = 0x00000000;
+ }
+
+ port->OTYPER = 0x00000000;
+ port->AFRL = 0x00000000;
+ port->AFRH = 0x00000000;
+ port->ODR = 0x00000000;
+}
+
+/*
+ * See header file
+ */
+void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
+{
+ /* prevent overwrite false reg entry */
+ init.pins = intercept_overwrite_register(port, init.pins);
+
+ /* process mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
+
+ /* process pull up/down resitors */
+ port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
+{
+ /* treat like input */
+ hal_gpio_init_input(port, init);
+
+ /* change mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
+{
+ /* prevent overwrite false reg entry */
+ init.pins = intercept_overwrite_register(port, init.pins);
+
+ /* process mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
+
+ /* process pull up/down resitors */
+ port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
+
+ /* process port speed */
+ port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
+
+ /* process output typ */
+ port->OTYPER &= ~init.pins;
+ if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
+ port->OTYPER |= init.pins;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_init_alternate(reg_gpio_t *port,
+ hal_gpio_af_t af_mode,
+ hal_gpio_output_t init)
+{
+ /* treat like output */
+ hal_gpio_init_output(port, init);
+
+ /* change mode */
+ port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
+ port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
+
+ /* process af type */
+ port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
+ port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
+ port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
+ port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
+}
+
+
+/*
+ * See header file
+ */
+uint16_t hal_gpio_input_read(reg_gpio_t *port)
+{
+ return (uint16_t) port->IDR;
+}
+
+
+/*
+ * See header file
+ */
+uint16_t hal_gpio_output_read(reg_gpio_t *port)
+{
+ return (uint16_t) port->ODR;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
+{
+ /* prevent overwrite false reg entry */
+ port_value = intercept_overwrite_register(port, port_value);
+ port->ODR = port_value;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
+{
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ port->BSRR = pins;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
+{
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ port->BSRR = (pins << 16);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
+{
+ uint16_t pattern;
+
+ /* prevent overwrite false reg entry */
+ pins = intercept_overwrite_register(port, pins);
+
+ /* exit if no pins to be configured */
+ if (pins != 0) {
+ /* get actual value and invert */
+ pattern = hal_gpio_output_read(port);
+ pattern = ~pattern;
+
+ /* mask pins */
+ pattern &= pins;
+
+ port->ODR = pattern;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_irq_set(reg_gpio_t *port,
+ uint16_t pins,
+ hal_gpio_trg_t edge,
+ hal_bool_t status)
+{
+ uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
+ uint32_t exticr_mask;
+
+ for (exti_line = 0u; exti_line < 16u; exti_line++) {
+ if (pins & (0x1 << exti_line)) {
+ syscfg_bank = exti_line / 4u;
+ syscfg_shift = exti_line % 4u;
+ nvic_bank = (exti_line < 10u) ? 0u : 1u;
+
+ if (status == ENABLE) {
+ /* Trigger (rising/falling/both) */
+ if (edge & HAL_GPIO_TRG_POS) {
+ EXTI->RTSR |= (0x1 << exti_line);
+ }
+ if (edge & HAL_GPIO_TRG_NEG) {
+ EXTI->FTSR |= (0x1 << exti_line);
+ }
+ /* Set EXTI line to corresponding GPIO port */
+ exticr_mask = get_syscfg_mask(port);
+ if (syscfg_bank == 0u) {
+ SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 1u) {
+ SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 2u) {
+ SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
+ } else if (syscfg_bank == 3u) {
+ SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
+ SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
+ }
+
+ /* Unmask interrupt */
+ EXTI->IMR |= (0x1 << exti_line);
+ if (nvic_bank == 0u) {
+ NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 1u) {
+ NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 2u) {
+ NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ }
+
+ } else {
+ /* Mask interrupt */
+ EXTI->IMR &= ~(0x1 << exti_line);
+ if (nvic_bank == 0u) {
+ NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 1u) {
+ NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ } else if (nvic_bank == 2u) {
+ NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
+ (exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
+ }
+ }
+ }
+ }
+
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_gpio_irq_status(uint16_t pin)
+{
+ hal_bool_t status = DISABLED;
+
+ if ((EXTI->IMR && pin) &&
+ (EXTI->PR && pin)) {
+ status = ENABLED;
+ }
+
+ return status;
+}
+
+
+/*
+ * See header file
+ */
+void hal_gpio_irq_clear(uint16_t pin)
+{
+ EXTI->PR |= pin;
+}
+
+
+/* -- Local function definitions
+ * ------------------------------------------------------------------------- */
+
+/**
+ * \brief Creates a pattern based on specified pins.
+ *
+ * example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
+ * ==> pattern = 0x0000'0288
+ *
+ * 0b0..0'0001'1010 / 0b10 (2 bit wide)
+ * ^ ^ ^
+ * ==> 0b0..0'00010'1000'1000
+ * ^^ ^^ ^^
+ *
+ * pattern_bit_width must be 2 or 4
+ */
+static uint32_t create_pattern_mask(uint16_t pins,
+ uint8_t pattern,
+ uint8_t pattern_bit_width)
+{
+ const uint8_t mask_bit_width = 32u;
+ const uint16_t pin1_mask = 1u;
+
+ uint8_t pos, end;
+ uint32_t mask = 0u;
+
+ if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
+ /* create pattern mask */
+ end = mask_bit_width / pattern_bit_width;
+ for (pos = 0; pos < end; pos++) {
+ if (pins & pin1_mask) {
+ mask |= pattern << (pos * pattern_bit_width);
+ }
+ pins >>= 1;
+ }
+ } else {
+ /* exit if pattern_bit_width not as needed */
+ mask = 0u;
+ }
+
+ return mask;
+}
+
+
+/**
+ * \brief This function ensures that these sensitive pins are not reconfigured.
+ *
+ * On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
+ * Pins 15 down to 12 are used for system functions of the discovery board,
+ * e.g. connection of the debugger.
+ * These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
+ */
+static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
+ if (port == GPIOA || port == GPIOB){
+ pins &= 0x0FFF;
+ }
+ return pins;
+}
+
+
+/**
+ * \brief Returns mask for configuration of SYSCFG_EXTICR register.
+ * \param port : Port of which the mask should be generated.
+ * \return Mask for specified port.
+ */
+static uint8_t get_syscfg_mask(reg_gpio_t *port)
+{
+ return ((port == GPIOA) ? 0u :
+ (port == GPIOB) ? 1u :
+ (port == GPIOC) ? 2u :
+ (port == GPIOD) ? 3u :
+ (port == GPIOE) ? 4u :
+ (port == GPIOF) ? 5u :
+ (port == GPIOG) ? 6u :
+ (port == GPIOH) ? 7u :
+ (port == GPIOI) ? 8u :
+ (port == GPIOJ) ? 9u : 10u);
+}
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c
new file mode 100644
index 0000000..a244dd6
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_pwr.
+ *
+ * The hardware abstraction layer for the power control unit.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_pwr.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define TIME_OUT 0x1000
+#define MASK_PERIPH_PWR (1u << 28u)
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_pwr_reset(void)
+{
+ /* Reset peripheral */
+ PWR->CR = 0x0000c000;
+ PWR->CSR = 0x00000000;
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
+{
+ uint16_t count = 0;
+ uint32_t reg = 0;
+
+ if (status == DISABLE) {
+ /* Disable backup domain / regulator */
+ PWR->CSR &= ~(1u << 9u);
+ return DISABLED;
+ }
+
+ /* Enable backup domain / regulator */
+ PWR->CSR |= (1u << 9u);
+
+ /* Wait till regulator is ready and if time out is reached exit */
+ reg = PWR->CSR & (1u << 3u);
+ while ((reg == 0) && (count != TIME_OUT)) {
+ reg = PWR->CSR & (1u << 3u);
+ count++;
+ }
+
+ /* Return */
+ if (reg != 0) {
+ return ENABLED;
+ }
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_backup_access(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CR &= ~(1u << 8u);
+ } else {
+ PWR->CR |= (1u << 8u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_wakeup_pin(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CSR &= ~(1u << 8u);
+ } else {
+ PWR->CSR |= (1u << 8u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_pwr_set_flash_powerdown(hal_bool_t status)
+{
+ if (status == DISABLE) {
+ PWR->CR &= ~(1u << 9u);
+ } else {
+ PWR->CR |= (1u << 9u);
+ }
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
+{
+ /* Is this realy nedded ?
+ Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
+{
+ /* Is this realy nedded ? */
+ return DISABLED;
+}
diff --git a/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c
new file mode 100644
index 0000000..fdd4d3a
--- /dev/null
+++ b/arith_operations/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c
@@ -0,0 +1,347 @@
+/* ----------------------------------------------------------------------------
+ * -- _____ ______ _____ -
+ * -- |_ _| | ____|/ ____| -
+ * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
+ * -- | | | '_ \| __| \___ \ Zurich University of -
+ * -- _| |_| | | | |____ ____) | Applied Sciences -
+ * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+ * ------------------------------------------------------------------------- */
+/**
+ * \brief Implementation of module hal_rcc.
+ *
+ * The hardware abstraction layer for the reset and clock control unit.
+ *
+ * $Id$
+ * ------------------------------------------------------------------------- */
+
+/* User includes */
+#include "hal_rcc.h"
+#include "reg_stm32f4xx.h"
+
+
+/* -- Macros
+ * ------------------------------------------------------------------------- */
+
+#define TIME_OUT 0x5000
+
+
+/* -- Public function definitions
+ * ------------------------------------------------------------------------- */
+
+/*
+ * See header file
+ */
+void hal_rcc_reset(void)
+{
+ /* Set RCC->CR to default values */
+ RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
+ RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
+ // PLLSAI bits (STM32F42xx/43xx)
+ RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
+
+ /* Reset RCC->CFGR to default values */
+ RCC->CFGR = 0u;
+
+ /* Reset RCC->PLLxCFGR to default values */
+ RCC->PLLCFGR = 0x24003010;
+ RCC->PLLI2SCFGR = 0x20003000;
+ RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
+
+ /* Disable all interrupts */
+ RCC->CIR = 0u;
+
+ /* Disable all peripherals */
+ RCC->AHB1RSTR = 0u;
+ RCC->AHB2RSTR = 0u;
+ RCC->AHB3RSTR = 0u;
+ RCC->APB1RSTR = 0u;
+ RCC->APB2RSTR = 0u;
+ RCC->AHB1ENR = 0x00100000;
+ RCC->AHB2ENR = 0u;
+ RCC->AHB3ENR = 0u;
+ RCC->APB1ENR = 0u;
+ RCC->APB2ENR = 0u;
+ RCC->AHB1LPENR = 0x7e6791ff;
+ RCC->AHB2LPENR = 0x000000f1;
+ RCC->AHB3LPENR = 0x00000001;
+ RCC->APB1LPENR = 0x36fec9ff;
+ RCC->APB2LPENR = 0x00075f33;
+
+ /* Reset forgotten registers */
+ RCC->BDCR = 0u;
+ RCC->CSR = 0x0e000000;
+ RCC->SSCGR = 0u;
+ RCC->DCKCFGR = 0u;
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
+{
+ volatile uint32_t *reg;
+ uint32_t bit_pos;
+
+ /* Select correct enable register */
+ switch (peripheral) {
+ /* AHB1 */
+ case PER_GPIOA:
+ bit_pos = 0u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOB:
+ bit_pos = 1u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOC:
+ bit_pos = 2u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOD:
+ bit_pos = 3u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOE:
+ bit_pos = 4u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOF:
+ bit_pos = 5u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOG:
+ bit_pos = 6u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOH:
+ bit_pos = 7u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOI:
+ bit_pos = 8u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOJ:
+ bit_pos = 9u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_GPIOK:
+ bit_pos = 10u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_DMA1:
+ bit_pos = 21u;
+ reg = &RCC->AHB1ENR;
+ break;
+ case PER_DMA2:
+ bit_pos = 22u;
+ reg = &RCC->AHB1ENR;
+ break;
+
+ /* AHB3 */
+ case PER_FMC:
+ bit_pos = 0u;
+ reg = &RCC->AHB3ENR;
+ break;
+
+ /* APB1 */
+ case PER_DAC:
+ bit_pos = 29u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_PWR:
+ bit_pos = 28u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM2:
+ bit_pos = 0u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM3:
+ bit_pos = 1u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM4:
+ bit_pos = 2u;
+ reg = &RCC->APB1ENR;
+ break;
+ case PER_TIM5:
+ bit_pos = 3u;
+ reg = &RCC->APB1ENR;
+ break;
+
+
+ /* APB2 */
+ case PER_ADC1:
+ bit_pos = 8u;
+ reg = &RCC->APB2ENR;
+ break;
+ case PER_ADC2:
+ bit_pos = 9u;
+ reg = &RCC->APB2ENR;
+ break;
+ case PER_ADC3:
+ bit_pos = 10u;
+ reg = &RCC->APB2ENR;
+ break;
+
+ default:
+ return;
+ }
+
+ if (status == DISABLE) {
+ *reg &= ~(1u << bit_pos);
+ } else {
+ *reg |= (1u << bit_pos);
+ }
+}
+
+
+/*
+ * See header file
+ */
+hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
+{
+ uint32_t reg = 0;
+ uint32_t count = 0;
+
+ /* Disable source */
+ if (status == DISABLE) {
+ RCC->CR &= ~(1u << source);
+ return DISABLED;
+ }
+
+ /* If pll, check if source is ok */
+ if (source == HAL_RCC_OSC_PLL ||
+ source == HAL_RCC_OSC_PLLI2S ||
+ source == HAL_RCC_OSC_PLLSAI)
+ {
+ reg = RCC->CR;
+ /* HSE */
+ if (RCC->PLLCFGR & ~(1u << 22u)) {
+ reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
+ }
+ /* HSI */
+ else {
+ reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
+ }
+ /* Return if source is not ok */
+ if (!reg) {
+ return DISABLED;
+ }
+ }
+
+ /* Enable source */
+ RCC->CR |= (1u << source);
+
+ /* Wait till source is ready and if time out is reached exit */
+ reg = RCC->CR & (1u << (source + 1u));
+ while ((reg == 0) && (count != TIME_OUT)) {
+ reg = RCC->CR & (1u << (source + 1u));
+ count++;
+ }
+
+ /* Return */
+ if (reg != 0) {
+ return ENABLED;
+ }
+ return DISABLED;
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
+{
+ /* Input check */
+ if (init.m_divider < 2u) init.m_divider = 2u;
+
+ if (init.n_factor < 2u) init.n_factor = 2u;
+ if (init.n_factor > 432u) init.n_factor = 432u;
+
+ if (init.p_divider > 8u) init.p_divider = 8u;
+
+ if (init.q_divider < 2u) init.q_divider = 2u;
+
+ init.r_divider &= 0x07;
+
+ /* Set source or return if invalid */
+ if (init.source == HAL_RCC_OSC_HSI) {
+ RCC->PLLCFGR &= ~(1u << 22u);
+ } else if (init.source == HAL_RCC_OSC_HSE) {
+ RCC->PLLCFGR |= (1u << 22u);
+ } else {
+ return;
+ }
+
+ /* Set pll preescaler */
+ RCC->PLLCFGR &= ~(0x3f);
+ RCC->PLLCFGR |= init.m_divider;
+
+ /* Configure pll */
+ switch (pll) {
+ case HAL_RCC_OSC_PLL:
+ RCC->PLLCFGR &= ~0x0f037fc0;
+ RCC->PLLCFGR |= (init.n_factor << 6u);
+ RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
+ RCC->PLLCFGR |= (init.q_divider << 24u);
+ break;
+
+ case HAL_RCC_OSC_PLLI2S:
+ RCC->PLLI2SCFGR &= ~0x7f007fc0;
+ RCC->PLLI2SCFGR |= (init.n_factor << 6u);
+ RCC->PLLI2SCFGR |= (init.q_divider << 24u);
+ RCC->PLLI2SCFGR |= (init.r_divider << 28u);
+ break;
+
+/* case HAL_RCC_OSC_PLLSAI:
+ RCC->PLLSAICFGR &= ~0x7f007fc0;
+ RCC->PLLSAICFGR |= (init.n_factor << 6u);
+ RCC->PLLSAICFGR |= (init.q_divider << 24u);
+ RCC->PLLSAICFGR |= (init.r_divider << 28u);
+ break;
+*/
+ default:
+ break;
+ }
+}
+
+
+/*
+ * See header file
+ */
+void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
+{
+ uint32_t reg = 0;
+
+ /* Configure clock divider */
+ RCC->CFGR &= ~0x0000fcf0;
+ RCC->CFGR |= (init.hpre << 4u);
+ RCC->CFGR |= (init.ppre1 << 10u);
+ RCC->CFGR |= (init.ppre2 << 13u);
+
+ /* Select system clock source */
+ RCC->CFGR &= ~0x00000003;
+ switch (init.osc) {
+ default:
+ case HAL_RCC_OSC_HSI:
+ reg = 0u;
+ break;
+
+ case HAL_RCC_OSC_HSE:
+ reg = 1u;
+ break;
+
+ case HAL_RCC_OSC_PLL:
+ reg = 2u;
+ break;
+ }
+ RCC->CFGR |= reg;
+
+#ifndef TESTING
+ /* Wait till system clock is selected */
+ while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
+#endif
+}
diff --git a/arith_operations/RTE/_Target_1/RTE_Components.h b/arith_operations/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 0000000..08165c1
--- /dev/null
+++ b/arith_operations/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,15 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'arith_operations'
+ * Target: 'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/arith_operations/arith_operations.uvguix.roman b/arith_operations/arith_operations.uvguix.roman
new file mode 100644
index 0000000..ddb9482
--- /dev/null
+++ b/arith_operations/arith_operations.uvguix.roman
@@ -0,0 +1,1878 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+
+
+
+
+
+
+ 38003
+ Registers
+ 140 90
+
+
+ 346
+ Code Coverage
+ 1010 160
+
+
+ 204
+ Performance Analyzer
+ 1170
+
+
+
+
+
+ 35141
+ Event Statistics
+
+ 200 50 700
+
+
+ 1506
+ Symbols
+
+ 80 80 80
+
+
+ 1936
+ Watch 1
+
+ 200 133 133
+
+
+ 1937
+ Watch 2
+
+ 200 133 133
+
+
+ 1935
+ Call Stack + Locals
+
+ 200 133 133
+
+
+ 2506
+ Trace Data
+
+ 75 135 130 95 70 230 200 150
+
+
+ 466
+ Source Browser
+ 500
+ 300
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ -1
+
+
+
+
+
+
+ 44
+ 2
+ 3
+
+ -32000
+ -32000
+
+
+ -1
+ -1
+
+
+ -24
+ 157
+ 1597
+ 735
+
+
+
+ 0
+
+ 275
+ 0100000004000000010000000100000001000000010000000000000002000000000000000100000001000000000000002800000028000000010000000100000000000000010000004D433A5C55736572735C726F6D616E5C446F63756D656E74735C4C61625F355F41726974686D4F7065726174696F6E735C61726974685F6F7065726174696F6E735C6170705C61726974686D2E73000000000861726974686D2E7300000000C5D4F200FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000F4000000660000008007000069030000
+
+
+
+ 0
+ Build
+
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F40000004F00000090050000DF000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1005
+ 1005
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000ED00000039030000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 109
+ 109
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000ED00000039030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 1465
+ 1465
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 000000002D02000090050000BD020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1466
+ 1466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1467
+ 1467
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1468
+ 1468
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1506
+ 1506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ A3040000660000008D05000001010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 1913
+ 1913
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1935
+ 1935
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 03000000300200008D050000A4020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 1936
+ 1936
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 1937
+ 1937
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 1939
+ 1939
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1940
+ 1940
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1941
+ 1941
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 1942
+ 1942
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 195
+ 195
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000ED00000039030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 196
+ 196
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000ED00000039030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 197
+ 197
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 000000006A03000080070000E6030000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 198
+ 198
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 000000001902000090050000BD020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 199
+ 199
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006D0300008D050000CD030000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 203
+ 203
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ F40000006300000090050000DF000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 204
+ 204
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 221
+ 221
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000000000000000000000000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 2506
+ 2506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A0040000630000009005000029020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 2507
+ 2507
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 000000002D02000090050000A9020000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 343
+ 343
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 346
+ 346
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 35141
+ 35141
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F40000006300000090050000DF000000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35824
+ 35824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 35885
+ 35885
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35886
+ 35886
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35887
+ 35887
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35888
+ 35888
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35889
+ 35889
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35890
+ 35890
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35891
+ 35891
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35892
+ 35892
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35893
+ 35893
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35894
+ 35894
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35895
+ 35895
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35896
+ 35896
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35897
+ 35897
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35898
+ 35898
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35899
+ 35899
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35900
+ 35900
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35901
+ 35901
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35902
+ 35902
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35903
+ 35903
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35904
+ 35904
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 35905
+ 35905
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 38003
+ 38003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 0300000066000000ED000000A4020000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 38007
+ 38007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 000000006A03000090050000E6030000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 436
+ 436
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006D0300008D050000CD030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 437
+ 437
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 440
+ 440
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 463
+ 463
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006D0300008D050000CD030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 466
+ 466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000006D0300008D050000CD030000
+
+
+ 16
+ 560000006D00000072010000AD020000
+
+
+
+ 470
+ 470
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ F7000000660000008D050000C6000000
+
+
+ 16
+ 560000006D0000001E030000FD000000
+
+
+
+ 50000
+ 50000
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50001
+ 50001
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50002
+ 50002
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50003
+ 50003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50004
+ 50004
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50005
+ 50005
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50006
+ 50006
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50007
+ 50007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50008
+ 50008
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50009
+ 50009
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50010
+ 50010
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50011
+ 50011
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50012
+ 50012
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50013
+ 50013
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50014
+ 50014
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50015
+ 50015
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50016
+ 50016
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50017
+ 50017
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50018
+ 50018
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 50019
+ 50019
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ A3040000660000008D0500007C010000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 59392
+ 59392
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ 0000000000000000D10300001C000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59393
+ 0
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000E603000080070000F9030000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59399
+ 59399
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 1
+
+ 16
+ 000000001C000000E701000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59400
+ 59400
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 2
+
+ 16
+ 00000000380000006F02000054000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 824
+ 824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000300200008D05000090020000
+
+
+ 16
+ 560000006D0000004601000038010000
+
+
+
+ 3312
+ 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFF4000000DF00000090050000E3000000000000000100001004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000560000006D0000001E030000FD000000F40000004F00000090050000DF0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF9C0400004F000000A004000029020000000000000200001004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000560000006D0000004601000038010000A00400004F000000900500002902000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFF00000004F000000F400000052030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C40000007394000001800010000001000000560000006D0000004601000038010000000000004F000000F0000000520300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000015020000900500001902000000000000010000100400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000000000000560000006D0000004601000038010000000000001902000090050000BD02000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFC802000019020000CC020000BD02000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF00000000520300008007000056030000010000000100001004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000560000006D0000001E030000FD000000000000005603000080070000E60300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000
+
+
+ 59392
+ File
+
+ 2556
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000004000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000036634309600000000000000020003663430035041440000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000000000000010000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65FF7F0000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000
+
+
+
+ 59399
+ Build
+
+ 976
+ 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64FF7F0000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000
+
+
+
+ 59400
+ Debug
+
+ 2373
+ 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000000000000100000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000000000001000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000000000000100000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000000000000100000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000000000000100000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F720100000000000000000000000100000001000000000000000000000001000000000000000000054465627567FF7F0000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000
+
+
+
+ 0
+ 1920
+ 1080
+
+
+
+
+
+ 1
+ 0
+
+ 100
+ 0
+
+ .\app\arithm.s
+ 0
+ 42
+ 1
+ 1
+
+ 0
+
+
+
+
+
diff --git a/sum_diff/sum_diff.uvguix.roman b/sum_diff/sum_diff.uvguix.roman
index e4645b9..5c4498b 100644
--- a/sum_diff/sum_diff.uvguix.roman
+++ b/sum_diff/sum_diff.uvguix.roman
@@ -1822,7 +1822,7 @@
Build
976
- 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000002001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+ 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
583
@@ -1838,7 +1838,7 @@
Debug
2373
- 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+ 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
898
@@ -3547,7 +3547,7 @@
File
2556
- 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000036634309600000000000000020003663430035041440000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000300150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000400160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000036634309600000000000000020003663430035041440000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000300150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
1423
@@ -3563,7 +3563,7 @@
Build
955
- 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+ 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
583
@@ -3579,7 +3579,7 @@
Debug
2362
- 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+ 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
898
@@ -3606,9 +3606,9 @@
0
.\app\sumdiff.s
- 47
+ 0
25
- 65
+ 59
1
0