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Schrom01 2022-10-14 09:51:31 +02:00
parent 92504d1fb6
commit e1d9b30ed0
47 changed files with 11502 additions and 11 deletions
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9
table_asm/EventRecorderStub.scvd Normal file
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

100
table_asm/RTE/Device/CT_Board_HS14_M0/.datainit_ctboard.s@4.0.1 Normal file
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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

439
table_asm/RTE/Device/CT_Board_HS14_M0/.startup_ctboard.s@4.0.1 Normal file
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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

290
table_asm/RTE/Device/CT_Board_HS14_M0/.system_ctboard.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

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;* ------------------------------------------------------------------
;* -- _____ ______ _____ -
;* -- |_ _| | ____|/ ____| -
;* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
;* -- | | | '_ \| __| \___ \ Zurich University of -
;* -- _| |_| | | | |____ ____) | Applied Sciences -
;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
;* ------------------------------------------------------------------
;* --
;* -- Project : CT Board - Cortex M4
;* -- Description : Data Segment initialisation.
;* --
;* -- $Id$
;* ------------------------------------------------------------------
; -------------------------------------------------------------------
; -- __Main
; -------------------------------------------------------------------
AREA |.text|, CODE, READONLY
IMPORT main
EXPORT __main
__main PROC
; initialize RW and ZI data - this includes heap and stack for the -ro=... -rw=... -entry=... linking cmd args...
IMPORT |Image$$RO$$Limit| [WEAK]
IMPORT |Image$$RW$$Base| [WEAK]
IMPORT |Image$$ZI$$Base| [WEAK]
IMPORT |Image$$ZI$$Limit| [WEAK]
; ...or from auto generated scatter file. Needs linker option: --diag_suppress 6314
IMPORT |Image$$ER_IROM1$$Limit| [WEAK]
IMPORT |Image$$RW_IRAM1$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Base| [WEAK]
IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [WEAK]
; import stack parameter
IMPORT Stack_Size [WEAK]
IMPORT Stack_Mem [WEAK]
; switch between command line generated regions and auto scatter file generated regions
LDR R1, =|Image$$RO$$Limit|
CMP R1,#0
BEQ ScatterFileSymbols
CommandLineSymbols
LDR R2, =|Image$$RW$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
ScatterFileSymbols
LDR R1, =|Image$$ER_IROM1$$Limit| ; start of flashed initial RW data
LDR R2, =|Image$$RW_IRAM1$$Base| ; start of the RW data in RAM
LDR R3, =|Image$$RW_IRAM1$$ZI$$Base| ; end of the RW data in RAM
MOV R5, R3 ; start of zero initialized data
LDR R6, =|Image$$RW_IRAM1$$ZI$$Limit| ; end of zero initialized data
B CondRWLoop
; init non-zero data
LoopRWCopy LDR R4, [R1]
STR R4, [R2]
ADDS R1, R1, #4
ADDS R2, R2, #4
CondRWLoop CMP R2, R3
BNE LoopRWCopy
; init zero-initialized data
MOV R2, R5
MOV R3, R6
MOVS R4, #0
B CondZILoop
LoopZICopy STR R4, [R2]
ADDS R2, R2, #4
CondZILoop CMP R2, R3
BNE LoopZICopy
; fingerprint stack section
LDR R0, =Stack_Mem
LDR R1, =Stack_Size
LDR R2, =0xEFBEADDE ; stack fingerprint (little endian!)
LoopStack STR R2, [R0]
ADDS R0, R0, #4
SUBS R1, #4
BNE LoopStack
; go to the user main function
LDR R0, =main
BX R0
ENDP
; -------------------------------------------------------------------
; -- End of file
; -------------------------------------------------------------------
ALIGN
END

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;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f429_439xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 08-November-2013
;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM/SDRAM mounted
;* on STM324x9I-EVAL boards to be used as data memory
;* (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT Stack_Size
EXPORT Stack_Mem
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __system
IMPORT __main
ENTRY
LDR R0, =__system
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Interface of module system_ctboard.
* Description : Basic system configuration.
* * initialize system clock
* * initialize FMC (SRAM & GPIO)
*
* GPIO FMC pin assignment:
*
* PD0 > FMC_D2 | PE0 > FMC_NBL0 | PF0 > FMC_A0 | PG0 > FMC_A10
* PD1 > FMC_D3 | PE1 > FMC_NBL1 | PF1 > FMC_A1 | PG1 > FMC_A11
* PD3 > FMC_CLK | PE2 > FMC_A23 | PF2 > FMC_A2 | PG2 > FMC_A12
* PD4 > FMC_NOE | PE3 > FMC_A19 | PF3 > FMC_A3 | PG3 > FMC_A13
* PD5 > FMC_NWE | PE4 > FMC_A20 | PF4 > FMC_A4 | PG4 > FMC_A14
* PD6 > FMC_WAIT | PE5 > FMC_A21 | PF5 > FMC_A5 | PG5 > FMC_A15
* PD7 > FMC_NE1 | PE6 > FMC_A22 | PF12 > FMC_A6 | PG9 > FMC_NE2
* PD8 > FMC_D13 | PE7 > FMC_D4 | PF13 > FMC_A7 | PG10 > FMC_NE3
* PD9 > FMC_D14 | PE8 > FMC_D5 | PF14 > FMC_A8 | PG12 > FMC_NE4
* PD10 > FMC_A15 | PE9 > FMC_D6 | PF15 > FMC_A9 | PG13 > FMC_A24
* PD11 > FMC_A16 | PE10 > FMC_D7 | |
* PD12 > FMC_A17 | PE11 > FMC_D8 | |
* PD13 > FMC_A18 | PE12 > FMC_D9 | |
* PD14 > FMC_D0 | PE13 > FMC_D10 | |
* PD15 > FMC_D1 | PE14 > FMC_D11 | |
* | PE15 > FMC_D12 | |
*
* $Id$
* ------------------------------------------------------------------------- */
/* Standard includes */
#include <stdint.h>
/* User includes */
#include "system_ctboard.h"
#include "reg_stm32f4xx.h"
#include "reg_ctboard.h"
/* -- Macros (LCD)
* ------------------------------------------------------------------------- */
#define LCD_WAIT 0x1fff
/* -- Macros (FMC)
* ------------------------------------------------------------------------- */
#define FMC_PORTD_PINMASK 0xfffb
#define FMC_PORTE_PINMASK 0xffff
#define FMC_PORTF_PINMASK 0xf03f
#define FMC_PORTG_PINMASK 0x363f
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static void init_SystemClock(void);
static void init_FPU(void);
static void init_FMC_SRAM(void);
static void init_LCD(void);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Entry point used in startup.
*/
void __system(void)
{
system_enter_run();
}
/*
* See header files
*/
void system_enter_run(void)
{
/* Initialize RCC / system clock */
init_SystemClock();
/* Iitialize FPU */
init_FPU();
/* Initialize SRAM interface */
init_FMC_SRAM();
/* Initialize LCD on CT-Board */
init_LCD();
}
/*
* See header file
*/
void system_enter_sleep(hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_stop(hal_pwr_regulator_t regulator, hal_pwr_lp_entry_t entry)
{
/** \note Implement this function if needed. */
}
/*
* See header file
*/
void system_enter_standby(void)
{
/** \note Implement this function if needed. */
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Configures the System clock source, PLL Multiplier and Divider
* factors, AHB/APBx prescalers and Flash settings.
*/
static void init_SystemClock(void)
{
hal_rcc_pll_init_t pll_init;
hal_rcc_clk_init_t clk_init;
/* Enable used periphery */
PWR_ENABLE();
/* Reset */
hal_rcc_reset();
PWR_RESET();
/* Enable HSE oscillator and proceed if ok */
if (hal_rcc_set_osc(HAL_RCC_OSC_HSE, ENABLE)) {
/* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= 0x00000000;
PWR->CR |= 0x0000c000;
/* Configure PLL */
pll_init.source = HAL_RCC_OSC_HSE;
pll_init.m_divider = 4u;
pll_init.n_factor = 168u;
pll_init.p_divider = 2u;
pll_init.q_divider = 7u;
hal_rcc_setup_pll(HAL_RCC_OSC_PLL, pll_init);
/* Enable PLL */
hal_rcc_set_osc(HAL_RCC_OSC_PLL, ENABLE);
/* Enable overdrive to allow system clock >= 168 MHz */
hal_pwr_set_overdrive(ENABLE);
/* Configure Flash prefetch, Instruction cache, Data cache
* and wait state */
FLASH->ACR = 0x00000705;
/* Setup system clock */
clk_init.osc = HAL_RCC_OSC_PLL;
clk_init.hpre = HAL_RCC_HPRE_2; // -> AHB clock : 84 MHz
clk_init.ppre1 = HAL_RCC_PPRE_2; // -> APB1 clock : 48 MHz
clk_init.ppre2 = HAL_RCC_PPRE_2; // -> APB2 clock : 48 MHz
hal_rcc_setup_clock(clk_init);
} else {
/* If HSE fails to start-up, the application will have wrong clock con-
figuration. User can add here some code to deal with this error */
}
}
/**
* \brief Initialize the floating point unit in M4 mode.
*/
static void init_FPU(void)
{
#ifdef PLATFORM_M4
/* No documentation about this, even the registers... */
/* set CP10 and CP11 Full Access */
FPU->CPACR |= ((3u << 20u)|(3u << 22u));
#endif
}
/**
* \brief Setup the flexible memory controller. This function configures the SRAM
* interface for accessing the periphery on the CT Board.
*/
static void init_FMC_SRAM(void)
{
#ifndef NO_FMC
hal_gpio_output_t gpio_init;
hal_fmc_sram_init_t sram_init;
hal_fmc_sram_timing_t sram_timing;
/* Enable used peripherals */
GPIOD_ENABLE();
GPIOE_ENABLE();
GPIOF_ENABLE();
GPIOG_ENABLE();
FMC_ENABLE();
/* Configure the involved GPIO pins to AF12 (FMC) */
gpio_init.pupd = HAL_GPIO_PUPD_NOPULL;
gpio_init.out_speed = HAL_GPIO_OUT_SPEED_50MHZ;
gpio_init.out_type = HAL_GPIO_OUT_TYPE_PP;
/* GPIOD configuration (pins: 0,1,3-15) */
gpio_init.pins = FMC_PORTD_PINMASK;
hal_gpio_init_alternate(GPIOD, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOE configuration (pins: 0-15) */
gpio_init.pins = FMC_PORTE_PINMASK;
hal_gpio_init_alternate(GPIOE, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOF configuration (pins: 0-5,12-15) */
gpio_init.pins = FMC_PORTF_PINMASK;
hal_gpio_init_alternate(GPIOF, HAL_GPIO_AF_FMC, gpio_init);
/* GPIOG configuration (pins: 1-5, 9, 10, 12, 13) */
gpio_init.pins = FMC_PORTG_PINMASK;
hal_gpio_init_alternate(GPIOG, HAL_GPIO_AF_FMC, gpio_init);
/* Initialize the synchronous PSRAM on bank 1 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_PSRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = ENABLE;
sram_init.write_enable = ENABLE;
sram_init.write_burst = ENABLE;
sram_init.continous_clock = ENABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.clk_divider = 15u;
sram_timing.data_latency = 2u;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK1, sram_init, sram_timing);
/* Initialize the asynchronous SRAM on bank 2 */
sram_init.address_mux = DISABLE;
sram_init.type = HAL_FMC_TYPE_SRAM;
sram_init.width = HAL_FMC_WIDTH_16B;
sram_init.read_burst = DISABLE;
sram_init.write_enable = DISABLE;
sram_init.write_burst = DISABLE;
sram_init.continous_clock = DISABLE;
sram_timing.bus_turnaround = 1u;
sram_timing.address_setup = 11u;
sram_timing.address_hold = 5u;
sram_timing.data_setup = 11u;
sram_timing.mode = HAL_FMC_ACCESS_MODE_A;
hal_fmc_init_sram(HAL_FMC_SRAM_BANK2, sram_init, sram_timing);
#endif
}
/**
* \brief Wait for the LCD controller on the CT Board to be initialized.
* \TODO Possibly adjust LCD controller on CPLD to set status bit
* and wait for it in this function.
*/
static void init_LCD(void)
{
#ifndef NO_FMC
uint32_t wait_for_lcd = LCD_WAIT;
for(; wait_for_lcd > 0; wait_for_lcd--);
#endif
}

143
table_asm/RTE/HAL/CT_Board_HS14_M0/.hal_fmc.c@3.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

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table_asm/RTE/HAL/CT_Board_HS14_M0/.hal_gpio.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

132
table_asm/RTE/HAL/CT_Board_HS14_M0/.hal_pwr.c@2.2.0 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

347
table_asm/RTE/HAL/CT_Board_HS14_M0/.hal_rcc.c@4.0.1 Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

143
table_asm/RTE/HAL/CT_Board_HS14_M0/hal_fmc.c Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_fmc.
*
* The hardware abstraction layer for the memory controller.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_fmc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define MASK_PERIPH_FMC (0x00000001)
#define MASK_SRAM_ENABLE (0x00000001)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_fmc_reset(hal_fmc_bank_t bank)
{
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = 0x000030db;
FMC->SRAM.BTR1 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = 0x000030d2;
FMC->SRAM.BTR2 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = 0x000030d2;
FMC->SRAM.BTR3 = 0x0fffffff;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = 0x000030d2;
FMC->SRAM.BTR4 = 0x0fffffff;
break;
}
}
/*
* See header file
*/
void hal_fmc_init_sram(hal_fmc_bank_t bank,
hal_fmc_sram_init_t init,
hal_fmc_sram_timing_t timing)
{
uint32_t reg_cr = 0, reg_tr = 0;
/* Input check */
timing.address_setup &= 0xf;
timing.address_hold &= 0xf;
if (timing.address_hold < 1u) timing.address_hold = 1u;
timing.data_setup &= 0xff;
if (timing.data_setup < 1u) timing.data_setup = 1u;
timing.bus_turnaround &= 0xf;
/* Input check clock divider (2..16) */
if (timing.clk_divider > 16u) timing.clk_divider = 16u;
if (timing.clk_divider < 2u) timing.clk_divider = 2u;
timing.clk_divider -= 1u; // 0b0001 -> clk / 2
/* Input check data latency (2..17) */
if (timing.data_latency > 17u) timing.data_latency = 17u;
if (timing.data_latency < 2u) timing.data_latency = 2u;
timing.data_latency -= 2u; // 0b0000 -> latency = 2
/* Process boolean parameter */
if (init.address_mux == ENABLE) reg_cr |= (1u << 1u);
if (init.read_burst == ENABLE) reg_cr |= (1u << 8u);
if (init.write_enable == ENABLE) reg_cr |= (1u << 12u);
if (init.write_burst == ENABLE) reg_cr |= (1u << 19u);
if (init.continous_clock == ENABLE) reg_cr |= (1u << 20u);
/* Process non boolean parameter */
reg_cr |= (init.type << 2u);
reg_cr |= (init.width << 4u);
/* Process timing for async. SRAM */
if (init.type == HAL_FMC_TYPE_SRAM) {
reg_tr |= (timing.address_setup << 0u);
reg_tr |= (timing.address_hold << 4u);
reg_tr |= (timing.data_setup << 8u);
reg_tr |= (timing.mode << 28u);
}
/* Process timing for sync. PSRAM */
else if (init.type == HAL_FMC_TYPE_PSRAM) {
reg_tr |= (timing.clk_divider << 20u);
reg_tr |= (timing.data_latency << 24u);
}
/* Process bus turnaround time */
reg_tr |= (timing.bus_turnaround << 16u);
/* Write register */
switch (bank) {
default:
case HAL_FMC_SRAM_BANK1:
FMC->SRAM.BCR1 = reg_cr;
FMC->SRAM.BTR1 = reg_tr;
FMC->SRAM.BCR1 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK2:
FMC->SRAM.BCR2 = reg_cr;
FMC->SRAM.BTR2 = reg_tr;
FMC->SRAM.BCR2 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK3:
FMC->SRAM.BCR3 = reg_cr;
FMC->SRAM.BTR3 = reg_tr;
FMC->SRAM.BCR3 |= MASK_SRAM_ENABLE;
break;
case HAL_FMC_SRAM_BANK4:
FMC->SRAM.BCR4 = reg_cr;
FMC->SRAM.BTR4 = reg_tr;
FMC->SRAM.BCR4 |= MASK_SRAM_ENABLE;
break;
}
}

412
table_asm/RTE/HAL/CT_Board_HS14_M0/hal_gpio.c Normal file
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/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_gpio.
*
* The hardware abstraction layer for the GPIO periphery.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_gpio.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define NVIC_OFFSET_1_4 ( 6u)
#define NVIC_OFFSET_5_9 (23u)
#define NVIC_OFFSET_10_15 ( 8u)
/* -- Local function declarations
* ------------------------------------------------------------------------- */
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width);
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins);
static uint8_t get_syscfg_mask(reg_gpio_t *port);
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_gpio_reset(reg_gpio_t *port)
{
if(port == GPIOA) {
/* Reset GPIOA specific values */
port->MODER = 0xa8000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x64000000;
}
else if (port == GPIOB) {
/* Reset GPIOB specific values */
port->MODER = 0x00000280;
port->OSPEEDR = 0x000000c0;
port->PUPDR = 0x00000100;
} else {
/* Reset other GPIO */
port->MODER = 0x00000000;
port->OSPEEDR = 0x00000000;
port->PUPDR = 0x00000000;
}
port->OTYPER = 0x00000000;
port->AFRL = 0x00000000;
port->AFRH = 0x00000000;
port->ODR = 0x00000000;
}
/*
* See header file
*/
void hal_gpio_init_input(reg_gpio_t *port, hal_gpio_input_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_IN, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
}
/*
* See header file
*/
void hal_gpio_init_analog(reg_gpio_t *port, hal_gpio_input_t init)
{
/* treat like input */
hal_gpio_init_input(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AN, 2u);
}
/*
* See header file
*/
void hal_gpio_init_output(reg_gpio_t *port, hal_gpio_output_t init)
{
/* prevent overwrite false reg entry */
init.pins = intercept_overwrite_register(port, init.pins);
/* process mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_OUT, 2u);
/* process pull up/down resitors */
port->PUPDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->PUPDR |= create_pattern_mask(init.pins, init.pupd, 2u);
/* process port speed */
port->OSPEEDR &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->OSPEEDR |= create_pattern_mask(init.pins, init.out_speed, 2u);
/* process output typ */
port->OTYPER &= ~init.pins;
if(init.out_type == HAL_GPIO_OUT_TYPE_OD){
port->OTYPER |= init.pins;
}
}
/*
* See header file
*/
void hal_gpio_init_alternate(reg_gpio_t *port,
hal_gpio_af_t af_mode,
hal_gpio_output_t init)
{
/* treat like output */
hal_gpio_init_output(port, init);
/* change mode */
port->MODER &= ~create_pattern_mask(init.pins, 0x3, 2u);
port->MODER |= create_pattern_mask(init.pins, HAL_GPIO_MODE_AF, 2u);
/* process af type */
port->AFRL &= ~create_pattern_mask(init.pins, 0xf, 4u);
port->AFRL |= create_pattern_mask(init.pins, af_mode, 4u);
port->AFRH &= ~create_pattern_mask((init.pins >> 8), 0xf, 4u);
port->AFRH |= create_pattern_mask((init.pins >> 8), af_mode, 4u);
}
/*
* See header file
*/
uint16_t hal_gpio_input_read(reg_gpio_t *port)
{
return (uint16_t) port->IDR;
}
/*
* See header file
*/
uint16_t hal_gpio_output_read(reg_gpio_t *port)
{
return (uint16_t) port->ODR;
}
/*
* See header file
*/
void hal_gpio_output_write(reg_gpio_t *port, uint16_t port_value)
{
/* prevent overwrite false reg entry */
port_value = intercept_overwrite_register(port, port_value);
port->ODR = port_value;
}
/*
* See header file
*/
void hal_gpio_bit_set(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = pins;
}
}
/*
* See header file
*/
void hal_gpio_bit_reset(reg_gpio_t *port, uint16_t pins)
{
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
port->BSRR = (pins << 16);
}
}
/*
* See header file
*/
void hal_gpio_bit_toggle(reg_gpio_t *port, uint16_t pins)
{
uint16_t pattern;
/* prevent overwrite false reg entry */
pins = intercept_overwrite_register(port, pins);
/* exit if no pins to be configured */
if (pins != 0) {
/* get actual value and invert */
pattern = hal_gpio_output_read(port);
pattern = ~pattern;
/* mask pins */
pattern &= pins;
port->ODR = pattern;
}
}
/*
* See header file
*/
void hal_gpio_irq_set(reg_gpio_t *port,
uint16_t pins,
hal_gpio_trg_t edge,
hal_bool_t status)
{
uint8_t syscfg_bank, nvic_bank, syscfg_shift, exti_line;
uint32_t exticr_mask;
for (exti_line = 0u; exti_line < 16u; exti_line++) {
if (pins & (0x1 << exti_line)) {
syscfg_bank = exti_line / 4u;
syscfg_shift = exti_line % 4u;
nvic_bank = (exti_line < 10u) ? 0u : 1u;
if (status == ENABLE) {
/* Trigger (rising/falling/both) */
if (edge & HAL_GPIO_TRG_POS) {
EXTI->RTSR |= (0x1 << exti_line);
}
if (edge & HAL_GPIO_TRG_NEG) {
EXTI->FTSR |= (0x1 << exti_line);
}
/* Set EXTI line to corresponding GPIO port */
exticr_mask = get_syscfg_mask(port);
if (syscfg_bank == 0u) {
SYSCFG->EXTICR1 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR1 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 1u) {
SYSCFG->EXTICR2 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR2 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 2u) {
SYSCFG->EXTICR3 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR3 |= (exticr_mask << syscfg_shift);
} else if (syscfg_bank == 3u) {
SYSCFG->EXTICR4 &= ~(0xf << syscfg_shift);
SYSCFG->EXTICR4 |= (exticr_mask << syscfg_shift);
}
/* Unmask interrupt */
EXTI->IMR |= (0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ISER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ISER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ISER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
} else {
/* Mask interrupt */
EXTI->IMR &= ~(0x1 << exti_line);
if (nvic_bank == 0u) {
NVIC->ICER0 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 1u) {
NVIC->ICER1 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
} else if (nvic_bank == 2u) {
NVIC->ICER2 |= ((exti_line < 5u) ? (0x1 << (exti_line + NVIC_OFFSET_1_4)) :
(exti_line < 10u) ? NVIC_OFFSET_5_9 : NVIC_OFFSET_10_15);
}
}
}
}
}
/*
* See header file
*/
hal_bool_t hal_gpio_irq_status(uint16_t pin)
{
hal_bool_t status = DISABLED;
if ((EXTI->IMR && pin) &&
(EXTI->PR && pin)) {
status = ENABLED;
}
return status;
}
/*
* See header file
*/
void hal_gpio_irq_clear(uint16_t pin)
{
EXTI->PR |= pin;
}
/* -- Local function definitions
* ------------------------------------------------------------------------- */
/**
* \brief Creates a pattern based on specified pins.
*
* example: pins = 1,3,4 (0x001a) / pattern = 0x2 (2 bit wide)
* ==> pattern = 0x0000'0288
*
* 0b0..0'0001'1010 / 0b10 (2 bit wide)
* ^ ^ ^
* ==> 0b0..0'00010'1000'1000
* ^^ ^^ ^^
*
* pattern_bit_width must be 2 or 4
*/
static uint32_t create_pattern_mask(uint16_t pins,
uint8_t pattern,
uint8_t pattern_bit_width)
{
const uint8_t mask_bit_width = 32u;
const uint16_t pin1_mask = 1u;
uint8_t pos, end;
uint32_t mask = 0u;
if (pattern_bit_width == 2u || pattern_bit_width == 4u) {
/* create pattern mask */
end = mask_bit_width / pattern_bit_width;
for (pos = 0; pos < end; pos++) {
if (pins & pin1_mask) {
mask |= pattern << (pos * pattern_bit_width);
}
pins >>= 1;
}
} else {
/* exit if pattern_bit_width not as needed */
mask = 0u;
}
return mask;
}
/**
* \brief This function ensures that these sensitive pins are not reconfigured.
*
* On GPIOA and GPIOB only pins 11 down to 0 are available to the user.
* Pins 15 down to 12 are used for system functions of the discovery board,
* e.g. connection of the debugger.
* These pins must not be reconfigured. Otherwise the debugger cannot be used any more.
*/
static uint16_t intercept_overwrite_register(reg_gpio_t *port, uint16_t pins){
if (port == GPIOA || port == GPIOB){
pins &= 0x0FFF;
}
return pins;
}
/**
* \brief Returns mask for configuration of SYSCFG_EXTICR register.
* \param port : Port of which the mask should be generated.
* \return Mask for specified port.
*/
static uint8_t get_syscfg_mask(reg_gpio_t *port)
{
return ((port == GPIOA) ? 0u :
(port == GPIOB) ? 1u :
(port == GPIOC) ? 2u :
(port == GPIOD) ? 3u :
(port == GPIOE) ? 4u :
(port == GPIOF) ? 5u :
(port == GPIOG) ? 6u :
(port == GPIOH) ? 7u :
(port == GPIOI) ? 8u :
(port == GPIOJ) ? 9u : 10u);
}

132
table_asm/RTE/HAL/CT_Board_HS14_M0/hal_pwr.c Normal file
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@ -0,0 +1,132 @@
/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_pwr.
*
* The hardware abstraction layer for the power control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_pwr.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x1000
#define MASK_PERIPH_PWR (1u << 28u)
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_pwr_reset(void)
{
/* Reset peripheral */
PWR->CR = 0x0000c000;
PWR->CSR = 0x00000000;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_backup_domain(hal_bool_t status)
{
uint16_t count = 0;
uint32_t reg = 0;
if (status == DISABLE) {
/* Disable backup domain / regulator */
PWR->CSR &= ~(1u << 9u);
return DISABLED;
}
/* Enable backup domain / regulator */
PWR->CSR |= (1u << 9u);
/* Wait till regulator is ready and if time out is reached exit */
reg = PWR->CSR & (1u << 3u);
while ((reg == 0) && (count != TIME_OUT)) {
reg = PWR->CSR & (1u << 3u);
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_pwr_set_backup_access(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 8u);
} else {
PWR->CR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_wakeup_pin(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CSR &= ~(1u << 8u);
} else {
PWR->CSR |= (1u << 8u);
}
}
/*
* See header file
*/
void hal_pwr_set_flash_powerdown(hal_bool_t status)
{
if (status == DISABLE) {
PWR->CR &= ~(1u << 9u);
} else {
PWR->CR |= (1u << 9u);
}
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_overdrive(hal_bool_t status)
{
/* Is this realy nedded ?
Extend clock to 180 MHz if HSI/HSE is used, but pll ? */
return DISABLED;
}
/*
* See header file
*/
hal_bool_t hal_pwr_set_underdrive(hal_bool_t status)
{
/* Is this realy nedded ? */
return DISABLED;
}

347
table_asm/RTE/HAL/CT_Board_HS14_M0/hal_rcc.c Normal file
View File

@ -0,0 +1,347 @@
/* ----------------------------------------------------------------------------
* -- _____ ______ _____ -
* -- |_ _| | ____|/ ____| -
* -- | | _ __ | |__ | (___ Institute of Embedded Systems -
* -- | | | '_ \| __| \___ \ Zurich University of -
* -- _| |_| | | | |____ ____) | Applied Sciences -
* -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
* ------------------------------------------------------------------------- */
/**
* \brief Implementation of module hal_rcc.
*
* The hardware abstraction layer for the reset and clock control unit.
*
* $Id$
* ------------------------------------------------------------------------- */
/* User includes */
#include "hal_rcc.h"
#include "reg_stm32f4xx.h"
/* -- Macros
* ------------------------------------------------------------------------- */
#define TIME_OUT 0x5000
/* -- Public function definitions
* ------------------------------------------------------------------------- */
/*
* See header file
*/
void hal_rcc_reset(void)
{
/* Set RCC->CR to default values */
RCC->CR |= 0x00000001; // Set HSION bit first -> keep cpu running
RCC->CR &= 0xeaf6ffff; // Reset HSEON, CSSON, PLLON, PLLI2S,
// PLLSAI bits (STM32F42xx/43xx)
RCC->CR &= 0xfffbffff; // Reset HSEBYP bit
/* Reset RCC->CFGR to default values */
RCC->CFGR = 0u;
/* Reset RCC->PLLxCFGR to default values */
RCC->PLLCFGR = 0x24003010;
RCC->PLLI2SCFGR = 0x20003000;
RCC->PLLSAICFGR = 0x24003000; // only STM32F42xx/43xx)
/* Disable all interrupts */
RCC->CIR = 0u;
/* Disable all peripherals */
RCC->AHB1RSTR = 0u;
RCC->AHB2RSTR = 0u;
RCC->AHB3RSTR = 0u;
RCC->APB1RSTR = 0u;
RCC->APB2RSTR = 0u;
RCC->AHB1ENR = 0x00100000;
RCC->AHB2ENR = 0u;
RCC->AHB3ENR = 0u;
RCC->APB1ENR = 0u;
RCC->APB2ENR = 0u;
RCC->AHB1LPENR = 0x7e6791ff;
RCC->AHB2LPENR = 0x000000f1;
RCC->AHB3LPENR = 0x00000001;
RCC->APB1LPENR = 0x36fec9ff;
RCC->APB2LPENR = 0x00075f33;
/* Reset forgotten registers */
RCC->BDCR = 0u;
RCC->CSR = 0x0e000000;
RCC->SSCGR = 0u;
RCC->DCKCFGR = 0u;
}
/*
* See header file
*/
void hal_rcc_set_peripheral(hal_peripheral_t peripheral, hal_bool_t status)
{
volatile uint32_t *reg;
uint32_t bit_pos;
/* Select correct enable register */
switch (peripheral) {
/* AHB1 */
case PER_GPIOA:
bit_pos = 0u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOB:
bit_pos = 1u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOC:
bit_pos = 2u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOD:
bit_pos = 3u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOE:
bit_pos = 4u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOF:
bit_pos = 5u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOG:
bit_pos = 6u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOH:
bit_pos = 7u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOI:
bit_pos = 8u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOJ:
bit_pos = 9u;
reg = &RCC->AHB1ENR;
break;
case PER_GPIOK:
bit_pos = 10u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA1:
bit_pos = 21u;
reg = &RCC->AHB1ENR;
break;
case PER_DMA2:
bit_pos = 22u;
reg = &RCC->AHB1ENR;
break;
/* AHB3 */
case PER_FMC:
bit_pos = 0u;
reg = &RCC->AHB3ENR;
break;
/* APB1 */
case PER_DAC:
bit_pos = 29u;
reg = &RCC->APB1ENR;
break;
case PER_PWR:
bit_pos = 28u;
reg = &RCC->APB1ENR;
break;
case PER_TIM2:
bit_pos = 0u;
reg = &RCC->APB1ENR;
break;
case PER_TIM3:
bit_pos = 1u;
reg = &RCC->APB1ENR;
break;
case PER_TIM4:
bit_pos = 2u;
reg = &RCC->APB1ENR;
break;
case PER_TIM5:
bit_pos = 3u;
reg = &RCC->APB1ENR;
break;
/* APB2 */
case PER_ADC1:
bit_pos = 8u;
reg = &RCC->APB2ENR;
break;
case PER_ADC2:
bit_pos = 9u;
reg = &RCC->APB2ENR;
break;
case PER_ADC3:
bit_pos = 10u;
reg = &RCC->APB2ENR;
break;
default:
return;
}
if (status == DISABLE) {
*reg &= ~(1u << bit_pos);
} else {
*reg |= (1u << bit_pos);
}
}
/*
* See header file
*/
hal_bool_t hal_rcc_set_osc(hal_rcc_osc_t source, hal_bool_t status)
{
uint32_t reg = 0;
uint32_t count = 0;
/* Disable source */
if (status == DISABLE) {
RCC->CR &= ~(1u << source);
return DISABLED;
}
/* If pll, check if source is ok */
if (source == HAL_RCC_OSC_PLL ||
source == HAL_RCC_OSC_PLLI2S ||
source == HAL_RCC_OSC_PLLSAI)
{
reg = RCC->CR;
/* HSE */
if (RCC->PLLCFGR & ~(1u << 22u)) {
reg &= (1u << (HAL_RCC_OSC_HSE + 1u));
}
/* HSI */
else {
reg &= (1u << (HAL_RCC_OSC_HSI + 1u));
}
/* Return if source is not ok */
if (!reg) {
return DISABLED;
}
}
/* Enable source */
RCC->CR |= (1u << source);
/* Wait till source is ready and if time out is reached exit */
reg = RCC->CR & (1u << (source + 1u));
while ((reg == 0) && (count != TIME_OUT)) {
reg = RCC->CR & (1u << (source + 1u));
count++;
}
/* Return */
if (reg != 0) {
return ENABLED;
}
return DISABLED;
}
/*
* See header file
*/
void hal_rcc_setup_pll(hal_rcc_osc_t pll, hal_rcc_pll_init_t init)
{
/* Input check */
if (init.m_divider < 2u) init.m_divider = 2u;
if (init.n_factor < 2u) init.n_factor = 2u;
if (init.n_factor > 432u) init.n_factor = 432u;
if (init.p_divider > 8u) init.p_divider = 8u;
if (init.q_divider < 2u) init.q_divider = 2u;
init.r_divider &= 0x07;
/* Set source or return if invalid */
if (init.source == HAL_RCC_OSC_HSI) {
RCC->PLLCFGR &= ~(1u << 22u);
} else if (init.source == HAL_RCC_OSC_HSE) {
RCC->PLLCFGR |= (1u << 22u);
} else {
return;
}
/* Set pll preescaler */
RCC->PLLCFGR &= ~(0x3f);
RCC->PLLCFGR |= init.m_divider;
/* Configure pll */
switch (pll) {
case HAL_RCC_OSC_PLL:
RCC->PLLCFGR &= ~0x0f037fc0;
RCC->PLLCFGR |= (init.n_factor << 6u);
RCC->PLLCFGR |= (((init.p_divider - 1) >> 1u) << 16u);
RCC->PLLCFGR |= (init.q_divider << 24u);
break;
case HAL_RCC_OSC_PLLI2S:
RCC->PLLI2SCFGR &= ~0x7f007fc0;
RCC->PLLI2SCFGR |= (init.n_factor << 6u);
RCC->PLLI2SCFGR |= (init.q_divider << 24u);
RCC->PLLI2SCFGR |= (init.r_divider << 28u);
break;
/* case HAL_RCC_OSC_PLLSAI:
RCC->PLLSAICFGR &= ~0x7f007fc0;
RCC->PLLSAICFGR |= (init.n_factor << 6u);
RCC->PLLSAICFGR |= (init.q_divider << 24u);
RCC->PLLSAICFGR |= (init.r_divider << 28u);
break;
*/
default:
break;
}
}
/*
* See header file
*/
void hal_rcc_setup_clock(hal_rcc_clk_init_t init)
{
uint32_t reg = 0;
/* Configure clock divider */
RCC->CFGR &= ~0x0000fcf0;
RCC->CFGR |= (init.hpre << 4u);
RCC->CFGR |= (init.ppre1 << 10u);
RCC->CFGR |= (init.ppre2 << 13u);
/* Select system clock source */
RCC->CFGR &= ~0x00000003;
switch (init.osc) {
default:
case HAL_RCC_OSC_HSI:
reg = 0u;
break;
case HAL_RCC_OSC_HSE:
reg = 1u;
break;
case HAL_RCC_OSC_PLL:
reg = 2u;
break;
}
RCC->CFGR |= reg;
#ifndef TESTING
/* Wait till system clock is selected */
while ((RCC->CFGR & 0x0000000c) != (reg << 2u));
#endif
}

15
table_asm/RTE/_Target_1/RTE_Components.h Normal file
View File

@ -0,0 +1,15 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'table'
* Target: 'Target 1'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */

43
table_asm/app/table.s
View File

@ -37,6 +37,8 @@ BITMASK_LOWER_NIBBLE EQU 0x0F
AREA MyAsmVar, DATA, READWRITE AREA MyAsmVar, DATA, READWRITE
; STUDENTS: To be programmed ; STUDENTS: To be programmed
store_table SPACE 16 ; reserve 16 byte (4 words)
@ -54,9 +56,50 @@ main PROC
readInput readInput
BL waitForKey ; wait for key to be pressed and released BL waitForKey ; wait for key to be pressed and released
; STUDENTS: To be programmed ; STUDENTS: To be programmed
; Read Valules from Dip Switches 7-0 to R0
LDR R0, =ADDR_DIP_SWITCH_7_0
LDRB R0, [R0]
; Write Values to LED 7-0 from R0
LDR R1, =ADDR_LED_7_0
STRB R0, [R1]
; Read Index from Dip Switches 15-8 to R1
LDR R1, =ADDR_DIP_SWITCH_15_8
LDRB R1, [R1]
LDR R2, =BITMASK_LOWER_NIBBLE
ANDS R1, R1, R2
; Write Index to LED 15-8 from R1
LDR R2, =ADDR_LED_15_8
STRB R1, [R2]
; Write Values to Store Table
LDR R2, =store_table
STRB R0, [R2, R1]
; Read Index from Dip Switches 15-8 to R1
; Todo: Maskierung
LDR R0, =ADDR_DIP_SWITCH_31_24
LDRB R0, [R0]
LDR R1, =BITMASK_LOWER_NIBBLE
ANDS R0, R0, R1
; Write Index to LED 15-8 from R1
LDR R1, =ADDR_LED_31_24
STRB R0, [R1]
; Read Values from Store Table
LDR R1, =store_table
LDRB R0, [R1, R0]
; Write Values to LED 7-0 from R0
LDR R1, =ADDR_LED_23_16
STRB R0, [R1]
; END: To be programmed ; END: To be programmed
B readInput B readInput

2
table_asm/build/ExtDll.iex Normal file
View File

@ -0,0 +1,2 @@
[EXTDLL]
Count=0

1
table_asm/build/datainit_ctboard.d Normal file
View File

@ -0,0 +1 @@
.\build\datainit_ctboard.o: RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s

372
table_asm/build/datainit_ctboard.lst Normal file
View File

@ -0,0 +1,372 @@
ARM Macro Assembler Page 1
1 00000000 ;* -----------------------------------------------------
-------------
2 00000000 ;* -- _____ ______ _____
-
3 00000000 ;* -- |_ _| | ____|/ ____|
-
4 00000000 ;* -- | | _ __ | |__ | (___ Institute of Embedded
Systems -
5 00000000 ;* -- | | | '_ \| __| \___ \ Zurich University of
-
6 00000000 ;* -- _| |_| | | | |____ ____) | Applied Sciences
-
7 00000000 ;* -- |_____|_| |_|______|_____/ 8401 Winterthur, Swit
zerland -
8 00000000 ;* -----------------------------------------------------
-------------
9 00000000 ;* --
10 00000000 ;* -- Project : CT Board - Cortex M4
11 00000000 ;* -- Description : Data Segment initialisation.
12 00000000 ;* --
13 00000000 ;* -- $Id$
14 00000000 ;* -----------------------------------------------------
-------------
15 00000000
16 00000000
17 00000000 ; ------------------------------------------------------
-------------
18 00000000 ; -- __Main
19 00000000 ; ------------------------------------------------------
-------------
20 00000000
21 00000000 AREA |.text|, CODE, READONLY
22 00000000
23 00000000 IMPORT main
24 00000000
25 00000000 EXPORT __main
26 00000000
27 00000000 __main PROC
28 00000000
29 00000000 ; initialize RW and ZI data - this includes heap and sta
ck for the -ro=... -rw=... -entry=... linking cmd args..
.
30 00000000 IMPORT |Image$$RO$$Limit| [WEAK]
31 00000000 IMPORT |Image$$RW$$Base| [WEAK]
32 00000000 IMPORT |Image$$ZI$$Base| [WEAK]
33 00000000 IMPORT |Image$$ZI$$Limit| [WEAK]
34 00000000 ; ...or from auto generated scatter file. Needs linker o
ption: --diag_suppress 6314
35 00000000 IMPORT |Image$$ER_IROM1$$Limit| [W
EAK]
36 00000000 IMPORT |Image$$RW_IRAM1$$Base| [W
EAK]
37 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Base| [W
EAK]
38 00000000 IMPORT |Image$$RW_IRAM1$$ZI$$Limit| [W
EAK]
39 00000000 ; import stack parameter
40 00000000 IMPORT Stack_Size [WEAK]
41 00000000 IMPORT Stack_Mem [WEAK]
ARM Macro Assembler Page 2
42 00000000
43 00000000 ; switch between command line generated regions and auto
scatter file generated regions
44 00000000 4912 LDR R1, =|Image$$RO$$Limit|
45 00000002 2900 CMP R1,#0
46 00000004 D004 BEQ ScatterFileSymbols
47 00000006 CommandLineSymbols
48 00000006 4A12 LDR R2, =|Image$$RW$$Base| ; start
of the RW data in R
AM
49 00000008 4B12 LDR R3, =|Image$$ZI$$Base| ; end of
the RW data in RAM
50 0000000A 461D MOV R5, R3 ; start of zero ini
tialized data
51 0000000C 4E12 LDR R6, =|Image$$ZI$$Limit| ; end o
f zero initialized
data
52 0000000E E009 B CondRWLoop
53 00000010 ScatterFileSymbols
54 00000010 4912 LDR R1, =|Image$$ER_IROM1$$Limit| ;
start of flashed i
nitial RW data
55 00000012 4A13 LDR R2, =|Image$$RW_IRAM1$$Base| ;
start of the RW dat
a in RAM
56 00000014 4B13 LDR R3, =|Image$$RW_IRAM1$$ZI$$Base
|
; end of the RW dat
a in RAM
57 00000016 461D MOV R5, R3 ; start of zero ini
tialized data
58 00000018 4E13 LDR R6, =|Image$$RW_IRAM1$$ZI$$Limi
t|
; end of zero initi
alized data
59 0000001A E003 B CondRWLoop
60 0000001C
61 0000001C ; init non-zero data
62 0000001C 680C LoopRWCopy
LDR R4, [R1]
63 0000001E 6014 STR R4, [R2]
64 00000020 1D09 ADDS R1, R1, #4
65 00000022 1D12 ADDS R2, R2, #4
66 00000024 429A CondRWLoop
CMP R2, R3
67 00000026 D1F9 BNE LoopRWCopy
68 00000028
69 00000028 ; init zero-initialized data
70 00000028 462A MOV R2, R5
71 0000002A 4633 MOV R3, R6
72 0000002C 2400 MOVS R4, #0
73 0000002E E001 B CondZILoop
74 00000030 6014 LoopZICopy
STR R4, [R2]
75 00000032 1D12 ADDS R2, R2, #4
76 00000034 429A CondZILoop
CMP R2, R3
77 00000036 D1FB BNE LoopZICopy
ARM Macro Assembler Page 3
78 00000038
79 00000038 ; fingerprint stack section
80 00000038 480C LDR R0, =Stack_Mem
81 0000003A 490D LDR R1, =Stack_Size
82 0000003C 4A0D LDR R2, =0xEFBEADDE ; stack fingerp
rint (little endian
!)
83 0000003E 6002 LoopStack
STR R2, [R0]
84 00000040 1D00 ADDS R0, R0, #4
85 00000042 3904 SUBS R1, #4
86 00000044 D1FB BNE LoopStack
87 00000046
88 00000046 ; go to the user main function
89 00000046 480C LDR R0, =main
90 00000048 4700 BX R0
91 0000004A ENDP
92 0000004A
93 0000004A
94 0000004A ; ------------------------------------------------------
-------------
95 0000004A ; -- End of file
96 0000004A ; ------------------------------------------------------
-------------
97 0000004A
98 0000004A 00 00 ALIGN
99 0000004C
100 0000004C END
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
EFBEADDE
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
ild\datainit_ctboard.d -o.\build\datainit_ctboard.o -I.\RTE\_Target_1 -IC:\User
s\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Us
ers\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -I
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --p
redefine="__EVAL SETA 1" --predefine="__UVISION_VERSION SETA 537" --predefine="
_RTE_ SETA 1" --predefine="_RTE_ SETA 1" --list=.\build\datainit_ctboard.lst RT
E/Device/CT_Board_HS14_M0/datainit_ctboard.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 21 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
None
Comment: .text unused
CommandLineSymbols 00000006
Symbol: CommandLineSymbols
Definitions
At line 47 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
None
Comment: CommandLineSymbols unused
CondRWLoop 00000024
Symbol: CondRWLoop
Definitions
At line 66 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 52 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
At line 59 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
CondZILoop 00000034
Symbol: CondZILoop
Definitions
At line 76 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 73 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: CondZILoop used once
LoopRWCopy 0000001C
Symbol: LoopRWCopy
Definitions
At line 62 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 67 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopRWCopy used once
LoopStack 0000003E
Symbol: LoopStack
Definitions
At line 83 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 86 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopStack used once
LoopZICopy 00000030
Symbol: LoopZICopy
Definitions
At line 74 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 77 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: LoopZICopy used once
ScatterFileSymbols 00000010
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Symbol: ScatterFileSymbols
Definitions
At line 53 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 46 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: ScatterFileSymbols used once
__main 00000000
Symbol: __main
Definitions
At line 27 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 25 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: __main used once
9 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
Image$$ER_IROM1$$Limit 00000000
Symbol: Image$$ER_IROM1$$Limit
Definitions
At line 35 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 54 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ER_IROM1$$Limit used once
Image$$RO$$Limit 00000000
Symbol: Image$$RO$$Limit
Definitions
At line 30 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 44 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RO$$Limit used once
Image$$RW$$Base 00000000
Symbol: Image$$RW$$Base
Definitions
At line 31 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 48 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW$$Base used once
Image$$RW_IRAM1$$Base 00000000
Symbol: Image$$RW_IRAM1$$Base
Definitions
At line 36 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 55 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$Base used once
Image$$RW_IRAM1$$ZI$$Base 00000000
Symbol: Image$$RW_IRAM1$$ZI$$Base
Definitions
At line 37 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 56 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$ZI$$Base used once
Image$$RW_IRAM1$$ZI$$Limit 00000000
Symbol: Image$$RW_IRAM1$$ZI$$Limit
Definitions
At line 38 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 58 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$RW_IRAM1$$ZI$$Limit used once
Image$$ZI$$Base 00000000
Symbol: Image$$ZI$$Base
Definitions
At line 32 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 49 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ZI$$Base used once
Image$$ZI$$Limit 00000000
Symbol: Image$$ZI$$Limit
ARM Macro Assembler Page 2 Alphabetic symbol ordering
External symbols
Definitions
At line 33 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 51 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Image$$ZI$$Limit used once
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 41 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 80 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Stack_Mem used once
Stack_Size 00000000
Symbol: Stack_Size
Definitions
At line 40 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 81 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: Stack_Size used once
main 00000000
Symbol: main
Definitions
At line 23 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Uses
At line 89 in file RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s
Comment: main used once
11 symbols
355 symbols in table

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./build/hal_fmc.o: RTE\HAL\CT_Board_HS14_M0\hal_fmc.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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./build/hal_gpio.o: RTE\HAL\CT_Board_HS14_M0\hal_gpio.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h

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./build/hal_pwr.o: RTE\HAL\CT_Board_HS14_M0\hal_pwr.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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./build/hal_rcc.o: RTE\HAL\CT_Board_HS14_M0\hal_rcc.c \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h

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.\build\startup_ctboard.o: RTE/Device/CT_Board_HS14_M0/startup_ctboard.s

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./build/system_ctboard.o: RTE\Device\CT_Board_HS14_M0\system_ctboard.c \
C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h \
C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h

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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.37.0.0
Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Roman Schenk, ZHAW, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.37.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCLANG\Bin
C Compiler: ArmClang.exe V6.18
Assembler: Armasm.exe V6.18
Linker/Locator: ArmLink.exe V6.18
Library Manager: ArmAr.exe V6.18
Hex Converter: FromElf.exe V6.18
CPU DLL: SARMCM3.DLL V5.37.0.0
Dialog DLL: DARMCM1.DLL V1.19.6.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.9.0
Dialog DLL: TARMCM1.DLL V1.14.6.0
<h2>Project:</h2>
C:\Users\roman\Documents\Lab_4_data_transfer\table_asm\table.uvprojx
Project File Date: 10/14/2022
<h2>Output:</h2>
*** Using Compiler 'V6.18', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
Rebuild target 'Target 1'
assembling table.s...
assembling datainit_ctboard.s...
assembling startup_ctboard.s...
compiling system_ctboard.c...
compiling hal_pwr.c...
compiling hal_fmc.c...
compiling hal_gpio.c...
compiling hal_rcc.c...
linking...
Program Size: Code=3520 RO-data=428 RW-data=16 ZI-data=8192
".\build\table.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: InES
https://ennis.zhaw.ch/pack/InES.CTBoard14_DFP.4.0.2.pack
InES.CTBoard14_DFP.4.0.2
CT Board 14 (STM32F429ZI) Device Support
* Component: Startup Version: 4.0.1
* Component: FMC Version: 3.0.1
* Component: GPIO Version: 4.0.1
* Component: PWR Version: 2.2.0
* Component: RCC Version: 4.0.1
<h2>Collection of Component include folders:</h2>
./RTE/_Target_1
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0
C:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include
<h2>Collection of Component Files used:</h2>
* Component: InES::Device:Startup:4.0.1
Include file: Device/Include/reg_ctboard.h
Include file: Device/Include/m0/platform_ctboard.h
Include file: Device/Include/reg_stm32f4xx.h
Include file: Device/Include/system_ctboard.h
Source file: Device/Source/datainit_ctboard.s
Source file: Device/Source/startup_ctboard.s
Source file: Device/Source/system_ctboard.c
* Component: InES::HAL:FMC:3.0.1
Include file: HAL/Include/hal_fmc.h
Include file: Device/Include/reg_stm32f4xx.h
Source file: HAL/Source/hal_fmc.c
Include file: HAL/Include/hal_common.h
* Component: InES::HAL:GPIO:4.0.1
Include file: HAL/Include/hal_gpio.h
Include file: HAL/Include/hal_common.h
Include file: Device/Include/reg_stm32f4xx.h
Source file: HAL/Source/hal_gpio.c
* Component: InES::HAL:PWR:2.2.0
Include file: HAL/Include/hal_pwr.h
Include file: HAL/Include/hal_common.h
Source file: HAL/Source/hal_pwr.c
Include file: Device/Include/reg_stm32f4xx.h
* Component: InES::HAL:RCC:4.0.1
Include file: HAL/Include/hal_rcc.h
Source file: HAL/Source/hal_rcc.c
Include file: HAL/Include/hal_common.h
Include file: Device/Include/reg_stm32f4xx.h
Build Time Elapsed: 00:00:00
</pre>
</body>
</html>

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.\build\table.o: app\table.s

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [.\build\table.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\build\table.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 6180002: Last Updated: Fri Oct 14 09:50:22 2022
<BR><P>
<H3>Maximum Stack Usage = 112 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
__system &rArr; system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
<LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
<LI><a href="#[3]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">MemManage_Handler</a><BR>
<LI><a href="#[4]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">BusFault_Handler</a><BR>
<LI><a href="#[5]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">UsageFault_Handler</a><BR>
<LI><a href="#[6]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[6]">SVC_Handler</a><BR>
<LI><a href="#[7]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[7]">DebugMon_Handler</a><BR>
<LI><a href="#[8]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[8]">PendSV_Handler</a><BR>
<LI><a href="#[9]">SysTick_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[9]">SysTick_Handler</a><BR>
<LI><a href="#[1c]">ADC_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC_IRQHandler</a><BR>
<LI><a href="#[65]">main</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[65]">main</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[1c]">ADC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4]">BusFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1e]">CAN1_RX0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1d]">CAN1_TX_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4a]">CAN2_RX0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4b]">CAN2_RX1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4c]">CAN2_SCE_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[49]">CAN2_TX_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[59]">CRYP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[58]">DCMI_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[15]">DMA1_Stream0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[16]">DMA1_Stream1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[17]">DMA1_Stream2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[18]">DMA1_Stream3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[19]">DMA1_Stream4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1a]">DMA1_Stream5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1b]">DMA1_Stream6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[39]">DMA1_Stream7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[64]">DMA2D_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[42]">DMA2_Stream0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[43]">DMA2_Stream1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[44]">DMA2_Stream2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[45]">DMA2_Stream3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[46]">DMA2_Stream4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4e]">DMA2_Stream5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4f]">DMA2_Stream6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[50]">DMA2_Stream7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[7]">DebugMon_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[47]">ETH_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[48]">ETH_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[e]">FLASH_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3a]">FMC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5b]">FPU_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5a]">HASH_RNG_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2]">HardFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[53]">I2C3_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[52]">I2C3_EV_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[63]">LTDC_ER_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[62]">LTDC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3]">MemManage_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[1]">NMI_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[4d]">OTG_FS_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[34]">OTG_FS_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[55]">OTG_HS_EP1_IN_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[54]">OTG_HS_EP1_OUT_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[57]">OTG_HS_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[56]">OTG_HS_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[b]">PVD_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[8]">PendSV_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[f]">RCC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[d]">RTC_WKUP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[0]">Reset_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[61]">SAI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3b]">SDIO_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3d]">SPI3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5e]">SPI4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5f]">SPI5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[60]">SPI6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[6]">SVC_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[9]">SysTick_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[c]">TAMP_STAMP_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[22]">TIM1_BRK_TIM9_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[25]">TIM1_CC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[24]">TIM1_TRG_COM_TIM11_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[23]">TIM1_UP_TIM10_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[26]">TIM2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[27]">TIM3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[28]">TIM4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3c]">TIM5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[40]">TIM6_DAC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[41]">TIM7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[35]">TIM8_BRK_TIM12_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[38]">TIM8_CC_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[37]">TIM8_TRG_COM_TIM14_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[36]">TIM8_UP_TIM13_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3e]">UART4_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[3f]">UART5_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5c]">UART7_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5d]">UART8_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[2f]">USART1_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[30]">USART2_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[31]">USART3_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[51]">USART6_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[5]">UsageFault_Handler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[a]">WWDG_IRQHandler</a> from startup_ctboard.o(.text) referenced from startup_ctboard.o(RESET)
<LI><a href="#[67]">__main</a> from datainit_ctboard.o(.text) referenced from startup_ctboard.o(.text)
<LI><a href="#[66]">__system</a> from system_ctboard.o(.text) referenced from startup_ctboard.o(.text)
<LI><a href="#[65]">main</a> from table.o(myCode) referenced from datainit_ctboard.o(.text)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[67]"></a>__main</STRONG> (Thumb, 74 bytes, Stack size 0 bytes, datainit_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(.text)
</UL>
<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4a]"></a>CAN2_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4b]"></a>CAN2_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4c]"></a>CAN2_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[49]"></a>CAN2_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[59]"></a>CRYP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[58]"></a>DCMI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>DMA1_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>DMA1_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>DMA1_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>DMA1_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>DMA1_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>DMA1_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>DMA1_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>DMA1_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[64]"></a>DMA2D_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>DMA2_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[43]"></a>DMA2_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[44]"></a>DMA2_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[45]"></a>DMA2_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[46]"></a>DMA2_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>DMA2_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4f]"></a>DMA2_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[50]"></a>DMA2_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[47]"></a>ETH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[48]"></a>ETH_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3a]"></a>FMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5b]"></a>FPU_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5a]"></a>HASH_RNG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[53]"></a>I2C3_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[52]"></a>I2C3_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[63]"></a>LTDC_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[62]"></a>LTDC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[4d]"></a>OTG_FS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>OTG_FS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[55]"></a>OTG_HS_EP1_IN_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[54]"></a>OTG_HS_EP1_OUT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[57]"></a>OTG_HS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[56]"></a>OTG_HS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>RTC_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[61]"></a>SAI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3b]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3d]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5e]"></a>SPI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5f]"></a>SPI5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[60]"></a>SPI6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>TAMP_STAMP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>TIM1_BRK_TIM9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>TIM1_TRG_COM_TIM11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[23]"></a>TIM1_UP_TIM10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3c]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[40]"></a>TIM6_DAC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[35]"></a>TIM8_BRK_TIM12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[38]"></a>TIM8_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[37]"></a>TIM8_TRG_COM_TIM14_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[36]"></a>TIM8_UP_TIM13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3e]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[3f]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5c]"></a>UART7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[5d]"></a>UART8_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[51]"></a>USART6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_ctboard.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(RESET)
</UL>
<P><STRONG><a name="[66]"></a>__system</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_ctboard.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = __system &rArr; system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_ctboard.o(.text)
</UL>
<P><STRONG><a name="[68]"></a>system_enter_run</STRONG> (Thumb, 240 bytes, Stack size 32 bytes, system_ctboard.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = system_enter_run &rArr; hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_fmc_init_sram
<LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_alternate
<LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_setup_clock
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_pwr_set_overdrive
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_setup_pll
<LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_set_osc
<LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_rcc_reset
</UL>
<BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__system
</UL>
<P><STRONG><a name="[71]"></a>system_enter_sleep</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[72]"></a>system_enter_stop</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[73]"></a>system_enter_standby</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, system_ctboard.o(.text), UNUSED)
<P><STRONG><a name="[74]"></a>hal_fmc_reset</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, hal_fmc.o(.text), UNUSED)
<P><STRONG><a name="[6f]"></a>hal_fmc_init_sram</STRONG> (Thumb, 324 bytes, Stack size 48 bytes, hal_fmc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = hal_fmc_init_sram
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[75]"></a>hal_gpio_reset</STRONG> (Thumb, 68 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[76]"></a>hal_gpio_init_input</STRONG> (Thumb, 156 bytes, Stack size 32 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[77]"></a>hal_gpio_init_analog</STRONG> (Thumb, 240 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[70]"></a>hal_gpio_init_output</STRONG> (Thumb, 284 bytes, Stack size 40 bytes, hal_gpio.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = hal_gpio_init_output
</UL>
<BR>[Called By]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_alternate
</UL>
<P><STRONG><a name="[6e]"></a>hal_gpio_init_alternate</STRONG> (Thumb, 248 bytes, Stack size 32 bytes, hal_gpio.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = hal_gpio_init_alternate &rArr; hal_gpio_init_output
</UL>
<BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;hal_gpio_init_output
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[78]"></a>hal_gpio_input_read</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[79]"></a>hal_gpio_output_read</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7a]"></a>hal_gpio_output_write</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7b]"></a>hal_gpio_bit_set</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7c]"></a>hal_gpio_bit_reset</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7d]"></a>hal_gpio_bit_toggle</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7e]"></a>hal_gpio_irq_set</STRONG> (Thumb, 292 bytes, Stack size 36 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[7f]"></a>hal_gpio_irq_status</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[80]"></a>hal_gpio_irq_clear</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, hal_gpio.o(.text), UNUSED)
<P><STRONG><a name="[81]"></a>hal_pwr_reset</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[82]"></a>hal_pwr_set_backup_domain</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[83]"></a>hal_pwr_set_backup_access</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[84]"></a>hal_pwr_set_wakeup_pin</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[85]"></a>hal_pwr_set_flash_powerdown</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[6c]"></a>hal_pwr_set_overdrive</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[86]"></a>hal_pwr_set_underdrive</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, hal_pwr.o(.text), UNUSED)
<P><STRONG><a name="[69]"></a>hal_rcc_reset</STRONG> (Thumb, 104 bytes, Stack size 16 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_rcc_reset
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[87]"></a>hal_rcc_set_peripheral</STRONG> (Thumb, 228 bytes, Stack size 8 bytes, hal_rcc.o(.text), UNUSED)
<P><STRONG><a name="[6a]"></a>hal_rcc_set_osc</STRONG> (Thumb, 108 bytes, Stack size 16 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_rcc_set_osc
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[6b]"></a>hal_rcc_setup_pll</STRONG> (Thumb, 192 bytes, Stack size 20 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = hal_rcc_setup_pll
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[6d]"></a>hal_rcc_setup_clock</STRONG> (Thumb, 92 bytes, Stack size 8 bytes, hal_rcc.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_rcc_setup_clock
</UL>
<BR>[Called By]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_enter_run
</UL>
<P><STRONG><a name="[65]"></a>main</STRONG> (Thumb, 76 bytes, Stack size 0 bytes, table.o(myCode))
<BR><BR>[Calls]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<BR>[Address Reference Count : 1]<UL><LI> datainit_ctboard.o(.text)
</UL><P>
<H3>
Local Symbols
</H3><P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>

13
table_asm/build/table.lnp Normal file
View File

@ -0,0 +1,13 @@
--cpu Cortex-M0
".\build\table.o"
".\build\datainit_ctboard.o"
".\build\startup_ctboard.o"
".\build\system_ctboard.o"
".\build\hal_fmc.o"
".\build\hal_gpio.o"
".\build\hal_pwr.o"
".\build\hal_rcc.o"
--strict --scatter ".\build\table.sct"
--diag_suppress 6314 --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\build\table.map" -o .\build\table.axf

404
table_asm/build/table.lst Normal file
View File

@ -0,0 +1,404 @@
ARM Macro Assembler Page 1
1 00000000 ; ------------------------------------------------------
------------
2 00000000 ; -- _____ ______ _____
-
3 00000000 ; -- |_ _| | ____|/ ____|
-
4 00000000 ; -- | | _ __ | |__ | (___ Institute of Embedded
Systems -
5 00000000 ; -- | | | '_ \| __| \___ \ Zurich University of
-
6 00000000 ; -- _| |_| | | | |____ ____) | Applied Sciences
-
7 00000000 ; -- |_____|_| |_|______|_____/ 8401 Winterthur, Switz
erland -
8 00000000 ; ------------------------------------------------------
------------
9 00000000 ; --
10 00000000 ; -- table.s
11 00000000 ; --
12 00000000 ; -- CT1 P04 Ein- und Ausgabe von Tabellenwerten
13 00000000 ; --
14 00000000 ; -- $Id: table.s 800 2014-10-06 13:19:25Z ruan $
15 00000000 ; ------------------------------------------------------
------------
16 00000000 ;Directives
17 00000000 PRESERVE8
18 00000000 THUMB
19 00000000 ; ------------------------------------------------------
------------
20 00000000 ; -- Symbolic Literals
21 00000000 ; ------------------------------------------------------
------------
22 00000000 60000200
ADDR_DIP_SWITCH_7_0
EQU 0x60000200
23 00000000 60000201
ADDR_DIP_SWITCH_15_8
EQU 0x60000201
24 00000000 60000203
ADDR_DIP_SWITCH_31_24
EQU 0x60000203
25 00000000 60000100
ADDR_LED_7_0
EQU 0x60000100
26 00000000 60000101
ADDR_LED_15_8
EQU 0x60000101
27 00000000 60000102
ADDR_LED_23_16
EQU 0x60000102
28 00000000 60000103
ADDR_LED_31_24
EQU 0x60000103
29 00000000 60000210
ADDR_BUTTONS
EQU 0x60000210
30 00000000
31 00000000 00000001
BITMASK_KEY_T0
ARM Macro Assembler Page 2
EQU 0x01
32 00000000 0000000F
BITMASK_LOWER_NIBBLE
EQU 0x0F
33 00000000
34 00000000 ; ------------------------------------------------------
------------
35 00000000 ; -- Variables
36 00000000 ; ------------------------------------------------------
------------
37 00000000 AREA MyAsmVar, DATA, READWRITE
38 00000000 ; STUDENTS: To be programmed
39 00000000
40 00000000 00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 store_table
SPACE 16 ; reserve 16 byte (
4 words)
41 00000010
42 00000010
43 00000010
44 00000010
45 00000010 ; END: To be programmed
46 00000010 ALIGN
47 00000010
48 00000010 ; ------------------------------------------------------
------------
49 00000010 ; -- myCode
50 00000010 ; ------------------------------------------------------
------------
51 00000010 AREA myCode, CODE, READONLY
52 00000000
53 00000000 main PROC
54 00000000 EXPORT main
55 00000000
56 00000000 readInput
57 00000000 F000 F818 BL waitForKey ; wait for key to b
e pressed and relea
sed
58 00000004 ; STUDENTS: To be programmed
59 00000004 ; Read Valules from Dip Switches 7-0 to R0
60 00000004 4811 LDR R0, =ADDR_DIP_SWITCH_7_0
61 00000006 7800 LDRB R0, [R0]
62 00000008
63 00000008 ; Write Values to LED 7-0 from R0
64 00000008 4911 LDR R1, =ADDR_LED_7_0
65 0000000A 7008 STRB R0, [R1]
66 0000000C
67 0000000C ; Read Index from Dip Switches 15-8 to R1
68 0000000C 4911 LDR R1, =ADDR_DIP_SWITCH_15_8
69 0000000E 7809 LDRB R1, [R1]
70 00000010 4A11 LDR R2, =BITMASK_LOWER_NIBBLE
71 00000012 4011 ANDS R1, R1, R2
72 00000014
73 00000014
74 00000014 ; Write Index to LED 15-8 from R1
ARM Macro Assembler Page 3
75 00000014 4A11 LDR R2, =ADDR_LED_15_8
76 00000016 7011 STRB R1, [R2]
77 00000018
78 00000018 ; Write Values to Store Table
79 00000018 4A11 LDR R2, =store_table
80 0000001A 5450 STRB R0, [R2, R1]
81 0000001C
82 0000001C
83 0000001C
84 0000001C ; Read Index from Dip Switches 15-8 to R1
85 0000001C ; Todo: Maskierung
86 0000001C 4811 LDR R0, =ADDR_DIP_SWITCH_31_24
87 0000001E 7800 LDRB R0, [R0]
88 00000020 490D LDR R1, =BITMASK_LOWER_NIBBLE
89 00000022 4008 ANDS R0, R0, R1
90 00000024
91 00000024 ; Write Index to LED 15-8 from R1
92 00000024 4910 LDR R1, =ADDR_LED_31_24
93 00000026 7008 STRB R0, [R1]
94 00000028
95 00000028 ; Read Values from Store Table
96 00000028 490D LDR R1, =store_table
97 0000002A 5C08 LDRB R0, [R1, R0]
98 0000002C
99 0000002C ; Write Values to LED 7-0 from R0
100 0000002C 490F LDR R1, =ADDR_LED_23_16
101 0000002E 7008 STRB R0, [R1]
102 00000030
103 00000030
104 00000030 ; END: To be programmed
105 00000030 E7E6 B readInput
106 00000032 00 00 ALIGN
107 00000034
108 00000034 ; ------------------------------------------------------
------------
109 00000034 ; Subroutines
110 00000034 ; ------------------------------------------------------
------------
111 00000034
112 00000034 ; wait for key to be pressed and released
113 00000034 waitForKey
114 00000034 B407 PUSH {R0, R1, R2}
115 00000036 490E LDR R1, =ADDR_BUTTONS ; laod base a
ddress of keys
116 00000038 4A0E LDR R2, =BITMASK_KEY_T0
; load key mask T0
117 0000003A
118 0000003A waitForPress
119 0000003A 7808 LDRB R0, [R1] ; load key values
120 0000003C 4210 TST R0, R2 ; check, if key T0
is pressed
121 0000003E D0FC BEQ waitForPress
122 00000040
123 00000040 waitForRelease
124 00000040 7808 LDRB R0, [R1] ; load key values
125 00000042 4210 TST R0, R2 ; check, if key T0
is released
126 00000044 D1FC BNE waitForRelease
127 00000046
ARM Macro Assembler Page 4
128 00000046 BC07 POP {R0, R1, R2}
129 00000048 4770 BX LR
130 0000004A 00 00 ALIGN
131 0000004C
132 0000004C ; ------------------------------------------------------
------------
133 0000004C ; End of code
134 0000004C ; ------------------------------------------------------
------------
135 0000004C ENDP
136 0000004C END
60000200
60000100
60000201
0000000F
60000101
00000000
60000203
60000103
60000102
60000210
00000001
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --depend=.\bu
ild\table.d -o.\build\table.o -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\
Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Loca
l\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData
\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --predefine="__EVAL SETA
1" --predefine="__UVISION_VERSION SETA 537" --predefine="_RTE_ SETA 1" --predef
ine="_RTE_ SETA 1" --list=.\build\table.lst app\table.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
MyAsmVar 00000000
Symbol: MyAsmVar
Definitions
At line 37 in file app\table.s
Uses
None
Comment: MyAsmVar unused
store_table 00000000
Symbol: store_table
Definitions
At line 40 in file app\table.s
Uses
At line 79 in file app\table.s
At line 96 in file app\table.s
2 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
main 00000000
Symbol: main
Definitions
At line 53 in file app\table.s
Uses
At line 54 in file app\table.s
Comment: main used once
myCode 00000000
Symbol: myCode
Definitions
At line 51 in file app\table.s
Uses
None
Comment: myCode unused
readInput 00000000
Symbol: readInput
Definitions
At line 56 in file app\table.s
Uses
At line 105 in file app\table.s
Comment: readInput used once
waitForKey 00000034
Symbol: waitForKey
Definitions
At line 113 in file app\table.s
Uses
At line 57 in file app\table.s
Comment: waitForKey used once
waitForPress 0000003A
Symbol: waitForPress
Definitions
At line 118 in file app\table.s
Uses
At line 121 in file app\table.s
Comment: waitForPress used once
waitForRelease 00000040
Symbol: waitForRelease
Definitions
At line 123 in file app\table.s
Uses
At line 126 in file app\table.s
Comment: waitForRelease used once
6 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
ADDR_BUTTONS 60000210
Symbol: ADDR_BUTTONS
Definitions
At line 29 in file app\table.s
Uses
At line 115 in file app\table.s
Comment: ADDR_BUTTONS used once
ADDR_DIP_SWITCH_15_8 60000201
Symbol: ADDR_DIP_SWITCH_15_8
Definitions
At line 23 in file app\table.s
Uses
At line 68 in file app\table.s
Comment: ADDR_DIP_SWITCH_15_8 used once
ADDR_DIP_SWITCH_31_24 60000203
Symbol: ADDR_DIP_SWITCH_31_24
Definitions
At line 24 in file app\table.s
Uses
At line 86 in file app\table.s
Comment: ADDR_DIP_SWITCH_31_24 used once
ADDR_DIP_SWITCH_7_0 60000200
Symbol: ADDR_DIP_SWITCH_7_0
Definitions
At line 22 in file app\table.s
Uses
At line 60 in file app\table.s
Comment: ADDR_DIP_SWITCH_7_0 used once
ADDR_LED_15_8 60000101
Symbol: ADDR_LED_15_8
Definitions
At line 26 in file app\table.s
Uses
At line 75 in file app\table.s
Comment: ADDR_LED_15_8 used once
ADDR_LED_23_16 60000102
Symbol: ADDR_LED_23_16
Definitions
At line 27 in file app\table.s
Uses
At line 100 in file app\table.s
Comment: ADDR_LED_23_16 used once
ADDR_LED_31_24 60000103
Symbol: ADDR_LED_31_24
Definitions
At line 28 in file app\table.s
Uses
At line 92 in file app\table.s
Comment: ADDR_LED_31_24 used once
ADDR_LED_7_0 60000100
Symbol: ADDR_LED_7_0
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Absolute symbols
Definitions
At line 25 in file app\table.s
Uses
At line 64 in file app\table.s
Comment: ADDR_LED_7_0 used once
BITMASK_KEY_T0 00000001
Symbol: BITMASK_KEY_T0
Definitions
At line 31 in file app\table.s
Uses
At line 116 in file app\table.s
Comment: BITMASK_KEY_T0 used once
BITMASK_LOWER_NIBBLE 0000000F
Symbol: BITMASK_LOWER_NIBBLE
Definitions
At line 32 in file app\table.s
Uses
At line 70 in file app\table.s
At line 88 in file app\table.s
10 symbols
353 symbols in table

372
table_asm/build/table.map Normal file
View File

@ -0,0 +1,372 @@
Component: Arm Compiler for Embedded 6.18 Tool: armlink [5e4cc100]
==============================================================================
Section Cross References
table.o(myCode) refers to table.o(MyAsmVar) for store_table
datainit_ctboard.o(.text) refers (Weak) to startup_ctboard.o(STACK) for Stack_Mem
datainit_ctboard.o(.text) refers to table.o(myCode) for main
startup_ctboard.o(RESET) refers to startup_ctboard.o(STACK) for __initial_sp
startup_ctboard.o(RESET) refers to startup_ctboard.o(.text) for Reset_Handler
startup_ctboard.o(.text) refers to system_ctboard.o(.text) for __system
startup_ctboard.o(.text) refers to datainit_ctboard.o(.text) for __main
system_ctboard.o(.text) refers to hal_rcc.o(.text) for hal_rcc_reset
system_ctboard.o(.text) refers to hal_pwr.o(.text) for hal_pwr_set_overdrive
system_ctboard.o(.text) refers to hal_gpio.o(.text) for hal_gpio_init_alternate
system_ctboard.o(.text) refers to hal_fmc.o(.text) for hal_fmc_init_sram
system_ctboard.o(.ARM.exidx) refers to system_ctboard.o(.text) for [Anonymous Symbol]
hal_fmc.o(.ARM.exidx) refers to hal_fmc.o(.text) for [Anonymous Symbol]
hal_gpio.o(.ARM.exidx) refers to hal_gpio.o(.text) for [Anonymous Symbol]
hal_pwr.o(.ARM.exidx) refers to hal_pwr.o(.text) for [Anonymous Symbol]
hal_rcc.o(.ARM.exidx) refers to hal_rcc.o(.text) for [Anonymous Symbol]
==============================================================================
Removing Unused input sections from the image.
Removing startup_ctboard.o(HEAP), (2048 bytes).
Removing system_ctboard.o(.ARM.exidx), (40 bytes).
Removing hal_fmc.o(.ARM.exidx), (16 bytes).
Removing hal_gpio.o(.ARM.exidx), (112 bytes).
Removing hal_pwr.o(.ARM.exidx), (56 bytes).
Removing hal_rcc.o(.ARM.exidx), (40 bytes).
6 unused section(s) (total 2312 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s 0x00000000 Number 0 datainit_ctboard.o ABSOLUTE
RTE/Device/CT_Board_HS14_M0/startup_ctboard.s 0x00000000 Number 0 startup_ctboard.o ABSOLUTE
app\table.s 0x00000000 Number 0 table.o ABSOLUTE
hal_fmc.c 0x00000000 Number 0 hal_fmc.o ABSOLUTE
hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE
hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE
hal_rcc.c 0x00000000 Number 0 hal_rcc.o ABSOLUTE
system_ctboard.c 0x00000000 Number 0 system_ctboard.o ABSOLUTE
RESET 0x08000000 Section 428 startup_ctboard.o(RESET)
.text 0x080001ac Section 124 datainit_ctboard.o(.text)
.text 0x08000228 Section 36 startup_ctboard.o(.text)
[Anonymous Symbol] 0x0800024c Section 0 system_ctboard.o(.text)
__arm_cp.1_0 0x08000344 Number 4 system_ctboard.o(.text)
__arm_cp.1_1 0x08000348 Number 4 system_ctboard.o(.text)
__arm_cp.1_2 0x0800034c Number 4 system_ctboard.o(.text)
__arm_cp.1_3 0x08000350 Number 4 system_ctboard.o(.text)
__arm_cp.1_4 0x08000354 Number 4 system_ctboard.o(.text)
__arm_cp.1_5 0x08000358 Number 4 system_ctboard.o(.text)
__arm_cp.1_6 0x0800035c Number 4 system_ctboard.o(.text)
__arm_cp.1_7 0x08000360 Number 4 system_ctboard.o(.text)
__arm_cp.1_8 0x08000364 Number 4 system_ctboard.o(.text)
__arm_cp.1_9 0x08000368 Number 4 system_ctboard.o(.text)
__arm_cp.1_10 0x0800036c Number 4 system_ctboard.o(.text)
__arm_cp.1_11 0x08000370 Number 4 system_ctboard.o(.text)
__arm_cp.1_12 0x08000374 Number 4 system_ctboard.o(.text)
__arm_cp.1_13 0x08000378 Number 4 system_ctboard.o(.text)
__arm_cp.1_14 0x0800037c Number 4 system_ctboard.o(.text)
__arm_cp.1_15 0x08000380 Number 4 system_ctboard.o(.text)
__arm_cp.1_16 0x08000384 Number 4 system_ctboard.o(.text)
__arm_cp.1_17 0x08000388 Number 4 system_ctboard.o(.text)
__arm_cp.1_18 0x0800038c Number 4 system_ctboard.o(.text)
[Anonymous Symbol] 0x08000398 Section 0 hal_fmc.o(.text)
__arm_cp.0_0 0x080003d4 Number 4 hal_fmc.o(.text)
__arm_cp.0_1 0x080003d8 Number 4 hal_fmc.o(.text)
__arm_cp.0_2 0x080003dc Number 4 hal_fmc.o(.text)
__arm_cp.1_0 0x08000524 Number 4 hal_fmc.o(.text)
__arm_cp.1_1 0x08000528 Number 4 hal_fmc.o(.text)
[Anonymous Symbol] 0x0800052c Section 0 hal_gpio.o(.text)
__arm_cp.0_0 0x08000570 Number 4 hal_gpio.o(.text)
__arm_cp.0_1 0x08000574 Number 4 hal_gpio.o(.text)
__arm_cp.1_0 0x08000614 Number 4 hal_gpio.o(.text)
__arm_cp.1_1 0x08000618 Number 4 hal_gpio.o(.text)
__arm_cp.2_0 0x0800070c Number 4 hal_gpio.o(.text)
__arm_cp.2_1 0x08000710 Number 4 hal_gpio.o(.text)
__arm_cp.3_0 0x08000830 Number 4 hal_gpio.o(.text)
__arm_cp.3_1 0x08000834 Number 4 hal_gpio.o(.text)
__arm_cp.7_0 0x08000950 Number 4 hal_gpio.o(.text)
__arm_cp.7_1 0x08000954 Number 4 hal_gpio.o(.text)
__arm_cp.8_0 0x08000970 Number 4 hal_gpio.o(.text)
__arm_cp.8_1 0x08000974 Number 4 hal_gpio.o(.text)
__arm_cp.9_0 0x08000994 Number 4 hal_gpio.o(.text)
__arm_cp.9_1 0x08000998 Number 4 hal_gpio.o(.text)
__arm_cp.10_0 0x080009b8 Number 4 hal_gpio.o(.text)
__arm_cp.10_1 0x080009bc Number 4 hal_gpio.o(.text)
__arm_cp.11_0 0x08000ae4 Number 4 hal_gpio.o(.text)
__arm_cp.11_1 0x08000ae8 Number 4 hal_gpio.o(.text)
__arm_cp.11_2 0x08000aec Number 4 hal_gpio.o(.text)
__arm_cp.11_3 0x08000af0 Number 4 hal_gpio.o(.text)
__arm_cp.11_4 0x08000af4 Number 4 hal_gpio.o(.text)
__arm_cp.11_5 0x08000af8 Number 4 hal_gpio.o(.text)
__arm_cp.12_0 0x08000b14 Number 4 hal_gpio.o(.text)
__arm_cp.13_0 0x08000b24 Number 4 hal_gpio.o(.text)
[Anonymous Symbol] 0x08000b28 Section 0 hal_pwr.o(.text)
__arm_cp.0_0 0x08000b38 Number 4 hal_pwr.o(.text)
__arm_cp.1_0 0x08000b74 Number 4 hal_pwr.o(.text)
__arm_cp.2_0 0x08000b90 Number 4 hal_pwr.o(.text)
__arm_cp.3_0 0x08000bac Number 4 hal_pwr.o(.text)
__arm_cp.4_0 0x08000bc8 Number 4 hal_pwr.o(.text)
[Anonymous Symbol] 0x08000bd4 Section 0 hal_rcc.o(.text)
__arm_cp.0_0 0x08000c3c Number 4 hal_rcc.o(.text)
__arm_cp.0_1 0x08000c40 Number 4 hal_rcc.o(.text)
__arm_cp.0_2 0x08000c44 Number 4 hal_rcc.o(.text)
__arm_cp.0_3 0x08000c48 Number 4 hal_rcc.o(.text)
__arm_cp.0_4 0x08000c4c Number 4 hal_rcc.o(.text)
__arm_cp.0_5 0x08000c50 Number 4 hal_rcc.o(.text)
__arm_cp.0_6 0x08000c54 Number 4 hal_rcc.o(.text)
__arm_cp.0_7 0x08000c58 Number 4 hal_rcc.o(.text)
__arm_cp.1_0 0x08000d40 Number 4 hal_rcc.o(.text)
__arm_cp.2_0 0x08000db0 Number 4 hal_rcc.o(.text)
__arm_cp.2_1 0x08000db4 Number 4 hal_rcc.o(.text)
__arm_cp.3_0 0x08000e78 Number 4 hal_rcc.o(.text)
__arm_cp.3_1 0x08000e7c Number 4 hal_rcc.o(.text)
__arm_cp.3_2 0x08000e80 Number 4 hal_rcc.o(.text)
__arm_cp.3_3 0x08000e84 Number 4 hal_rcc.o(.text)
__arm_cp.3_4 0x08000e88 Number 4 hal_rcc.o(.text)
__arm_cp.3_5 0x08000e8c Number 4 hal_rcc.o(.text)
__arm_cp.4_0 0x08000eec Number 4 hal_rcc.o(.text)
__arm_cp.4_1 0x08000ef0 Number 4 hal_rcc.o(.text)
myCode 0x08000ef4 Section 120 table.o(myCode)
store_table 0x20000000 Data 16 table.o(MyAsmVar)
MyAsmVar 0x20000000 Section 16 table.o(MyAsmVar)
STACK 0x20000010 Section 8192 startup_ctboard.o(STACK)
__initial_sp 0x20002010 Data 0 startup_ctboard.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
Image$$RO$$Limit - Undefined Weak Reference
Image$$RW$$Base - Undefined Weak Reference
Image$$ZI$$Base - Undefined Weak Reference
Image$$ZI$$Limit - Undefined Weak Reference
__Vectors_Size 0x000001ac Number 0 startup_ctboard.o ABSOLUTE
Stack_Size 0x00002000 Number 0 startup_ctboard.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_ctboard.o(RESET)
__Vectors_End 0x080001ac Data 0 startup_ctboard.o(RESET)
__main 0x080001ad Thumb Code 74 datainit_ctboard.o(.text)
Reset_Handler 0x08000229 Thumb Code 8 startup_ctboard.o(.text)
NMI_Handler 0x08000231 Thumb Code 2 startup_ctboard.o(.text)
HardFault_Handler 0x08000233 Thumb Code 2 startup_ctboard.o(.text)
MemManage_Handler 0x08000235 Thumb Code 2 startup_ctboard.o(.text)
BusFault_Handler 0x08000237 Thumb Code 2 startup_ctboard.o(.text)
UsageFault_Handler 0x08000239 Thumb Code 2 startup_ctboard.o(.text)
SVC_Handler 0x0800023b Thumb Code 2 startup_ctboard.o(.text)
DebugMon_Handler 0x0800023d Thumb Code 2 startup_ctboard.o(.text)
PendSV_Handler 0x0800023f Thumb Code 2 startup_ctboard.o(.text)
SysTick_Handler 0x08000241 Thumb Code 2 startup_ctboard.o(.text)
ADC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN1_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN1_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN1_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN1_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN2_RX0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN2_RX1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN2_SCE_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CAN2_TX_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
CRYP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DCMI_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA1_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2D_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
DMA2_Stream7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
ETH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
ETH_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI0_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI15_10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
EXTI9_5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
FLASH_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
FMC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
FPU_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
HASH_RNG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C1_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C1_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C2_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C2_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C3_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
I2C3_EV_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
LTDC_ER_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
LTDC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_FS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_FS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_EP1_IN_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_EP1_OUT_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
OTG_HS_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
PVD_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
RCC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
RTC_Alarm_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
RTC_WKUP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SAI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SDIO_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
SPI6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TAMP_STAMP_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM1_BRK_TIM9_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM1_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM1_TRG_COM_TIM11_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM1_UP_TIM10_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM6_DAC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM8_BRK_TIM12_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM8_CC_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM8_TRG_COM_TIM14_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
TIM8_UP_TIM13_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
UART4_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
UART5_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
UART7_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
UART8_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
USART1_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
USART2_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
USART3_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
USART6_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
WWDG_IRQHandler 0x08000243 Thumb Code 0 startup_ctboard.o(.text)
__system 0x0800024d Thumb Code 8 system_ctboard.o(.text)
system_enter_run 0x08000255 Thumb Code 240 system_ctboard.o(.text)
system_enter_sleep 0x08000391 Thumb Code 2 system_ctboard.o(.text)
system_enter_stop 0x08000393 Thumb Code 2 system_ctboard.o(.text)
system_enter_standby 0x08000395 Thumb Code 2 system_ctboard.o(.text)
hal_fmc_reset 0x08000399 Thumb Code 60 hal_fmc.o(.text)
hal_fmc_init_sram 0x080003e1 Thumb Code 324 hal_fmc.o(.text)
hal_gpio_reset 0x0800052d Thumb Code 68 hal_gpio.o(.text)
hal_gpio_init_input 0x08000579 Thumb Code 156 hal_gpio.o(.text)
hal_gpio_init_analog 0x0800061d Thumb Code 240 hal_gpio.o(.text)
hal_gpio_init_output 0x08000715 Thumb Code 284 hal_gpio.o(.text)
hal_gpio_init_alternate 0x08000839 Thumb Code 248 hal_gpio.o(.text)
hal_gpio_input_read 0x08000931 Thumb Code 6 hal_gpio.o(.text)
hal_gpio_output_read 0x08000937 Thumb Code 6 hal_gpio.o(.text)
hal_gpio_output_write 0x0800093d Thumb Code 20 hal_gpio.o(.text)
hal_gpio_bit_set 0x08000959 Thumb Code 24 hal_gpio.o(.text)
hal_gpio_bit_reset 0x08000979 Thumb Code 28 hal_gpio.o(.text)
hal_gpio_bit_toggle 0x0800099d Thumb Code 28 hal_gpio.o(.text)
hal_gpio_irq_set 0x080009c1 Thumb Code 292 hal_gpio.o(.text)
hal_gpio_irq_status 0x08000afd Thumb Code 24 hal_gpio.o(.text)
hal_gpio_irq_clear 0x08000b19 Thumb Code 12 hal_gpio.o(.text)
hal_pwr_reset 0x08000b29 Thumb Code 16 hal_pwr.o(.text)
hal_pwr_set_backup_domain 0x08000b3d Thumb Code 56 hal_pwr.o(.text)
hal_pwr_set_backup_access 0x08000b79 Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_wakeup_pin 0x08000b95 Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_flash_powerdown 0x08000bb1 Thumb Code 24 hal_pwr.o(.text)
hal_pwr_set_overdrive 0x08000bcd Thumb Code 4 hal_pwr.o(.text)
hal_pwr_set_underdrive 0x08000bd1 Thumb Code 4 hal_pwr.o(.text)
hal_rcc_reset 0x08000bd5 Thumb Code 104 hal_rcc.o(.text)
hal_rcc_set_peripheral 0x08000c5d Thumb Code 228 hal_rcc.o(.text)
hal_rcc_set_osc 0x08000d45 Thumb Code 108 hal_rcc.o(.text)
hal_rcc_setup_pll 0x08000db9 Thumb Code 192 hal_rcc.o(.text)
hal_rcc_setup_clock 0x08000e91 Thumb Code 92 hal_rcc.o(.text)
main 0x08000ef5 Thumb Code 76 table.o(myCode)
Image$$ER_IROM1$$Limit 0x08000f6c Number 0 anon$$obj.o ABSOLUTE
Image$$RW_IRAM1$$Base 0x20000000 Number 0 anon$$obj.o ABSOLUTE
Image$$RW_IRAM1$$ZI$$Base 0x20000010 Number 0 anon$$obj.o ABSOLUTE
Stack_Mem 0x20000010 Data 8192 startup_ctboard.o(STACK)
Image$$RW_IRAM1$$ZI$$Limit 0x20002010 Number 0 anon$$obj.o ABSOLUTE
==============================================================================
Memory Map of the image
Image Entry point : 0x08000229
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000f80, Max: 0x00200000, ABSOLUTE)
Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000f6c, Max: 0x00200000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x08000000 0x08000000 0x000001ac Data RO 14 RESET startup_ctboard.o
0x080001ac 0x080001ac 0x0000007c Code RO 8 .text datainit_ctboard.o
0x08000228 0x08000228 0x00000024 Code RO 15 * .text startup_ctboard.o
0x0800024c 0x0800024c 0x0000014a Code RO 19 .text system_ctboard.o
0x08000396 0x08000396 0x00000002 PAD
0x08000398 0x08000398 0x00000194 Code RO 27 .text hal_fmc.o
0x0800052c 0x0800052c 0x000005fc Code RO 35 .text hal_gpio.o
0x08000b28 0x08000b28 0x000000ac Code RO 43 .text hal_pwr.o
0x08000bd4 0x08000bd4 0x00000320 Code RO 51 .text hal_rcc.o
0x08000ef4 0x08000ef4 0x00000078 Code RO 2 myCode table.o
Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08000f70, Size: 0x00002010, Max: 0x00030000, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x20000000 0x08000f70 0x00000010 Data RW 1 MyAsmVar table.o
0x20000010 - 0x00002000 Zero RW 12 STACK startup_ctboard.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
124 50 0 0 0 412 datainit_ctboard.o
404 20 0 0 0 4171 hal_fmc.o
1532 96 0 0 0 12477 hal_gpio.o
172 20 0 0 0 2137 hal_pwr.o
800 168 0 0 0 5172 hal_rcc.o
36 8 428 0 8192 812 startup_ctboard.o
330 76 0 0 0 6760 system_ctboard.o
120 48 0 16 0 388 table.o
----------------------------------------------------------------------
3520 486 428 16 8192 32329 Object Totals
0 0 0 0 0 0 (incl. Generated)
2 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
0 0 0 0 0 0 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
3520 486 428 16 8192 32145 Grand Totals
3520 486 428 16 8192 32145 ELF Image Totals
3520 486 428 16 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 3948 ( 3.86kB)
Total RW Size (RW Data + ZI Data) 8208 ( 8.02kB)
Total ROM Size (Code + RO Data + RW Data) 3964 ( 3.87kB)
==============================================================================

BIN
table_asm/build/table.o Normal file
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16
table_asm/build/table.sct Normal file
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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}

36
table_asm/build/table_Target 1.dep Normal file
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@ -0,0 +1,36 @@
Dependencies for Project 'table', Target 'Target 1': (DO NOT MODIFY !)
CompilerVersion: 6180000::V6.18::ARMCLANG
F (.\app\table.s)(0x634914A7)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pd "__UVISION_VERSION SETA 537" --pd "_RTE_ SETA 1" --pd "_RTE_ SETA 1" --list .\build\table.lst --xref -o .\build\table.o --depend .\build\table.d)
F (RTE/Device/CT_Board_HS14_M0/datainit_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pd "__UVISION_VERSION SETA 537" --pd "_RTE_ SETA 1" --pd "_RTE_ SETA 1" --list .\build\datainit_ctboard.lst --xref -o .\build\datainit_ctboard.o --depend .\build\datainit_ctboard.d)
F (RTE/Device/CT_Board_HS14_M0/startup_ctboard.s)(0x5C517478)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g -I.\RTE\_Target_1 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0 -IC:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include --pd "__UVISION_VERSION SETA 537" --pd "_RTE_ SETA 1" --pd "_RTE_ SETA 1" --list .\build\startup_ctboard.lst --xref -o .\build\startup_ctboard.o --depend .\build\startup_ctboard.d)
F (RTE/Device/CT_Board_HS14_M0/system_ctboard.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/system_ctboard.o -MD)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\system_ctboard.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\m0\platform_ctboard.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_ctboard.h)(0x5C6AA868)
F (RTE/HAL/CT_Board_HS14_M0/hal_fmc.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_fmc.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_fmc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
F (RTE/HAL/CT_Board_HS14_M0/hal_gpio.c)(0x5C5ACEB0)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_gpio.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_gpio.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
F (RTE/HAL/CT_Board_HS14_M0/hal_pwr.c)(0x5C517478)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_pwr.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_pwr.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)
F (RTE/HAL/CT_Board_HS14_M0/hal_rcc.c)(0x5C597514)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m0 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -gdwarf-4 -O1 -fno-function-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I./RTE/_Target_1 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/Device/Include/m0 -IC:/Users/roman/AppData/Local/Arm/Packs/InES/CTBoard14_DFP/4.0.2/HAL/Include -D__UVISION_VERSION="537" -D_RTE_ -D_RTE_ -o ./build/hal_rcc.o -MD)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_rcc.h)(0x5C517478)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\HAL\Include\hal_common.h)(0x5C517478)
I (C:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6252B538)
I (C:\Users\roman\AppData\Local\Arm\Packs\InES\CTBoard14_DFP\4.0.2\Device\Include\reg_stm32f4xx.h)(0x5C597514)

3646
table_asm/table.uvguix.roman Normal file
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File diff suppressed because one or more lines are too long

28
table_asm/table.uvoptx
View File

@ -117,6 +117,26 @@
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon> <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt> </DebugOpt>
<TargetDriverDllRegistry> <TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry> <SetRegEntry>
<Number>0</Number> <Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key> <Key>ST-LINKIII-KEIL_SWO</Key>
@ -135,12 +155,12 @@
<DebugFlag> <DebugFlag>
<trace>0</trace> <trace>0</trace>
<periodic>0</periodic> <periodic>0</periodic>
<aLwin>0</aLwin> <aLwin>1</aLwin>
<aCover>0</aCover> <aCover>0</aCover>
<aSer1>0</aSer1> <aSer1>0</aSer1>
<aSer2>0</aSer2> <aSer2>0</aSer2>
<aPa>0</aPa> <aPa>0</aPa>
<viewmode>0</viewmode> <viewmode>1</viewmode>
<vrSel>0</vrSel> <vrSel>0</vrSel>
<aSym>0</aSym> <aSym>0</aSym>
<aTbox>0</aTbox> <aTbox>0</aTbox>
@ -196,7 +216,7 @@
<Group> <Group>
<GroupName>::Device</GroupName> <GroupName>::Device</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<RteFlg>1</RteFlg> <RteFlg>1</RteFlg>
@ -204,7 +224,7 @@
<Group> <Group>
<GroupName>::HAL</GroupName> <GroupName>::HAL</GroupName>
<tvExp>0</tvExp> <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<RteFlg>1</RteFlg> <RteFlg>1</RteFlg>

14
table_asm/table.uvprojx
View File

@ -447,7 +447,7 @@
</component> </component>
</components> </components>
<files> <files>
<file attr="config" category="source" name="Device\Source\datainit_ctboard.s"> <file attr="config" category="source" name="Device\Source\datainit_ctboard.s" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s</instance> <instance index="0">RTE\Device\CT_Board_HS14_M0\datainit_ctboard.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/> <component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -455,7 +455,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="Device\Source\startup_ctboard.s"> <file attr="config" category="source" name="Device\Source\startup_ctboard.s" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\startup_ctboard.s</instance> <instance index="0">RTE\Device\CT_Board_HS14_M0\startup_ctboard.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/> <component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -463,7 +463,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="Device\Source\system_ctboard.c"> <file attr="config" category="source" name="Device\Source\system_ctboard.c" version="4.0.1">
<instance index="0">RTE\Device\CT_Board_HS14_M0\system_ctboard.c</instance> <instance index="0">RTE\Device\CT_Board_HS14_M0\system_ctboard.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/> <component Cclass="Device" Cgroup="Startup" Cvendor="InES" Cversion="4.0.1" condition="SYSTEM_M0"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -471,7 +471,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="HAL\Source\hal_fmc.c"> <file attr="config" category="source" name="HAL\Source\hal_fmc.c" version="3.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_fmc.c</instance> <instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_fmc.c</instance>
<component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL"/> <component Cclass="HAL" Cgroup="FMC" Cvendor="InES" Cversion="3.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -479,7 +479,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="HAL\Source\hal_gpio.c"> <file attr="config" category="source" name="HAL\Source\hal_gpio.c" version="4.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_gpio.c</instance> <instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_gpio.c</instance>
<component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL"/> <component Cclass="HAL" Cgroup="GPIO" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -487,7 +487,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="HAL\Source\hal_pwr.c"> <file attr="config" category="source" name="HAL\Source\hal_pwr.c" version="2.2.0">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_pwr.c</instance> <instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_pwr.c</instance>
<component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL"/> <component Cclass="HAL" Cgroup="PWR" Cvendor="InES" Cversion="2.2.0" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>
@ -495,7 +495,7 @@
<targetInfo name="Target 1"/> <targetInfo name="Target 1"/>
</targetInfos> </targetInfos>
</file> </file>
<file attr="config" category="source" name="HAL\Source\hal_rcc.c"> <file attr="config" category="source" name="HAL\Source\hal_rcc.c" version="4.0.1">
<instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_rcc.c</instance> <instance index="0">RTE\HAL\CT_Board_HS14_M0\hal_rcc.c</instance>
<component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL"/> <component Cclass="HAL" Cgroup="RCC" Cvendor="InES" Cversion="4.0.1" condition="HAL"/>
<package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/> <package name="CTBoard14_DFP" schemaVersion="1.1" url="https://ennis.zhaw.ch/pack/" vendor="InES" version="4.0.2"/>